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ffff8000807fe308 t mbigen_write_msi_msg
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ffff8000807fe3a8 t mbigen_domain_translate
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ffff8000807fe948 t brcmstb_l2_intc_probe.isra.0
ffff8000807fec08 t brcmstb_l2_edge_intc_probe
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ffff8000807ff6b8 t mtk_cirq_domain_alloc
ffff8000807ff7f8 t mtk_cirq_resume
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ffff8000807ffec0 t irq_find_host
ffff8000807fff88 t mvebu_gicp_probe
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ffff800080800590 t mvebu_icu_probe
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ffff800080803e88 t mst_irq_resume
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ffff8000808043a8 t mst_intc_mask_irq
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ffff800080804588 t aic_irq_mask
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ffff800080804670 t aic_fiq_set_type
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ffff8000808046f8 t aic_irq_domain_translate
ffff800080804898 t aic_irq_domain_free
ffff800080804950 t aic_ipi_send_single
ffff800080804a08 t aic_handle_ipi.isra.0
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ffff800080804ca8 t aic_fiq_clear_mask.isra.0
ffff800080804d08 t aic_irq_set_affinity
ffff800080804eb0 t aic_irq_eoi
ffff800080804f38 t aic_fiq_unmask
ffff800080804fb0 t aic_fiq_eoi
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ffff8000808053d8 T cci_probed
ffff800080805438 t cci_platform_probe
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ffff8000808054f0 t hisi_lpc_acpi_remove_subdev
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ffff8000808055d8 t hisi_lpc_target_out
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ffff800080805dc8 t hisi_lpc_acpi_add_child
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ffff800080806308 t sun50i_de2_bus_remove
ffff800080806348 t sun50i_de2_bus_probe
ffff800080806428 t simple_pm_bus_runtime_resume
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ffff800080806548 t simple_pm_bus_resume
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ffff8000808068a8 t vexpress_config_devres_release
ffff800080806908 T devm_regmap_init_vexpress_config
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ffff800080807a28 t _of_phy_get
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ffff800080809ee8 T phy_mipi_dphy_get_default_config
ffff80008080a028 t phy_meson8b_usb2_probe
ffff80008080a248 t phy_meson8b_usb2_power_on
ffff80008080a568 t phy_meson8b_usb2_power_off
ffff80008080a648 t phy_meson_gxl_usb2_exit
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ffff80008080a8a8 t phy_meson_gxl_usb2_power_off
ffff80008080a928 t phy_meson_gxl_usb2_reset
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ffff80008080b488 t phy_g12a_usb3_pcie_cr_bus_write
ffff80008080b728 t phy_g12a_usb3_pcie_cr_bus_read
ffff80008080b8b0 t phy_g12a_usb3_pcie_probe
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ffff80008080bb88 t phy_g12a_usb3_pcie_init
ffff80008080bde8 t phy_g12a_mipi_dphy_analog_probe
ffff80008080bf10 t phy_g12a_mipi_dphy_analog_configure
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ffff80008080c148 t phy_axg_pcie_reset
ffff80008080c208 t phy_axg_pcie_exit
ffff80008080c258 t phy_axg_pcie_init
ffff80008080c2c8 t phy_axg_pcie_probe
ffff80008080c428 t phy_axg_pcie_power_on
ffff80008080c4c8 t phy_axg_pcie_power_off
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ffff80008080c690 t phy_dsi_analog_disable
ffff80008080c770 t phy_axg_mipi_pcie_analog_power_off
ffff80008080c858 t phy_dsi_analog_enable
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ffff80008080cba8 t phy_meson_axg_mipi_dphy_configure
ffff80008080ccd0 t phy_meson_axg_mipi_dphy_power_off
ffff80008080cd48 t phy_meson_axg_mipi_dphy_exit
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ffff80008080ee08 t exynos_dp_video_phy_power_off
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ffff80008098a0c8 t hi3798cv200_crg_probe
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ffff80008098a368 t hi3798cv200_sysctrl_clk_unregister
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ffff80008098bed8 T mtk_clk_simple_probe
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ffff80008098fa00 t readl
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ffff80008098fda8 t fhctl_hopping
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ffff800080990278 T fhctl_get_ops
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ffff800080990928 T mtk_clk_register_pllfhs
ffff800080990c20 T to_mtk_fh
ffff800080990c48 t clk_mt6765_ifr_probe
ffff800080990d58 t clk_mt6765_probe
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ffff800080990fc8 t clk_mt6765_top_probe
ffff800080991188 t clk_mt6779_top_probe
ffff8000809912b8 t clk_mt6779_apmixed_probe
ffff800080991378 t clk_mt6779_probe
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ffff8000809917d0 t clk_mt6795_infracfg_probe
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ffff8000809919b0 t clk_mt6795_pericfg_probe
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ffff800080991fe8 t clk_mt7988_apmixed_probe
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ffff800080993248 t clk_mt8195_apmixed_probe
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ffff8000809934a8 t clk_mt8195_topck_probe
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ffff8000809941e8 T meson_clk_hw_get
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ffff8000809943f8 T meson_clkc_mmio_probe
ffff800080994528 t meson_aoclk_do_reset
ffff800080994588 T meson_aoclkc_probe
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ffff8000809962d0 t meson_clk_pll_set_rate
ffff800080996568 T clk_regmap_init
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ffff800080997088 t meson_vclk_div_is_enabled
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ffff800080997398 t meson_vclk_gate_enable
ffff8000809974c8 t g12a_sys_pll_notifier_cb
ffff800080997558 t g12a_cpu_clk_mux_notifier_cb
ffff8000809975c8 t g12a_cpu_clk_dyn_notifier_cb
ffff800080997670 t g12a_dvfs_setup_common
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ffff800080997b68 T ap_cp_unique_name
ffff800080997c48 t armada_3700_xtal_clock_remove
ffff800080997c88 t armada_3700_xtal_clock_probe
ffff800080997e68 t armada_3700_tbg_clock_remove
ffff800080997ee8 t armada_3700_tbg_clock_probe
ffff8000809980e8 t armada_3700_periph_clock_resume
ffff800080998188 t armada_3700_periph_clock_remove
ffff800080998208 t armada_3700_periph_clock_probe
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ffff800080998ac8 t clk_pm_cpu_get_parent
ffff800080998bf0 t clk_pm_cpu_recalc_rate
ffff800080998d68 t ap806_syscon_common_probe
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ffff800080999918 t cp110_gate_enable
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ffff800080999a08 T rockchip_clk_finalize
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ffff80008099b608 t rockchip_rk3036_pll_wait_lock
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ffff80008099da48 T rockchip_clk_register_cpuclk
ffff80008099dd48 t rockchip_gate_grf_is_enabled
ffff80008099ddb8 t rockchip_gate_grf_enable
ffff80008099de48 t rockchip_gate_grf_disable
ffff80008099ded8 T rockchip_clk_register_gate_grf
ffff80008099e048 t clk_half_divider_set_rate
ffff80008099e168 t clk_half_divider_determine_rate
ffff80008099e378 t clk_half_divider_recalc_rate
ffff80008099e3e8 T rockchip_clk_register_halfdiv
ffff80008099e6e8 t rockchip_inv_set_phase
ffff80008099e838 t rockchip_inv_get_phase
ffff80008099e888 T rockchip_clk_register_inverter
ffff80008099e9e8 t rockchip_mmc_recalc
ffff80008099ea08 t rockchip_mmc_get_phase
ffff80008099eb50 t rockchip_mmc_set_phase
ffff80008099ece8 t rockchip_mmc_clk_rate_notify
ffff80008099edb8 T rockchip_clk_register_mmc
ffff80008099ef48 t rockchip_muxgrf_get_parent
ffff80008099f008 t rockchip_muxgrf_set_parent
ffff80008099f0c8 T rockchip_clk_register_muxgrf
ffff80008099f248 t rockchip_ddrclk_get_parent
ffff80008099f2a8 t rockchip_ddrclk_sip_set_rate
ffff80008099f398 t rockchip_ddrclk_sip_determine_rate
ffff80008099f468 t rockchip_ddrclk_sip_recalc_rate
ffff80008099f528 T rockchip_clk_register_ddrclk
ffff80008099f6e8 t rk_clk_gate_link_probe
ffff80008099f8c8 t rockchip_softrst_deassert
ffff80008099f9e8 T rockchip_register_softrst_lut
ffff80008099fae8 t rockchip_softrst_assert
ffff80008099fc08 T rk3528_rst_init
ffff80008099fc68 t clk_rk3562_probe
ffff80008099fce8 T rk3562_rst_init
ffff80008099fd48 t clk_rk3576_probe
ffff80008099fdc8 T rk3576_rst_init
ffff80008099fe28 t clk_rk3588_probe
ffff80008099fee8 T rk3588_rst_init
ffff80008099ff48 t samsung_clk_resume
ffff80008099ffd0 T samsung_clk_save
ffff8000809a0030 t samsung_clk_suspend
ffff8000809a00e8 T samsung_clk_restore
ffff8000809a0148 T samsung_clk_alloc_reg_dump
ffff8000809a0208 T samsung_clk_add_lookup
ffff8000809a0238 T samsung_clk_extended_sleep_init
ffff8000809a0348 t samsung_pll_determine_rate
ffff8000809a03c8 t samsung_pll_lock_wait
ffff8000809a04a8 t samsung_pll3xxx_disable
ffff8000809a04e8 t samsung_pll35xx_recalc_rate
ffff8000809a0528 t samsung_pll2550xx_recalc_rate
ffff8000809a0568 t samsung_pll2126_recalc_rate
ffff8000809a05b0 t samsung_pll3000_recalc_rate
ffff8000809a05f8 t samsung_pll3xxx_enable
ffff8000809a0668 t samsung_pll2550x_recalc_rate
ffff8000809a06b0 t samsung_pll45xx_recalc_rate
ffff8000809a0708 t samsung_pll6552_recalc_rate
ffff8000809a0788 t samsung_pll0822x_recalc_rate
ffff8000809a0828 t samsung_pll36xx_recalc_rate
ffff8000809a0878 t samsung_pll0831x_recalc_rate
ffff8000809a08c8 t samsung_pll2650x_recalc_rate
ffff8000809a0928 t samsung_pll6553_recalc_rate
ffff8000809a0988 t samsung_pll1031x_recalc_rate
ffff8000809a09e8 t samsung_pll2650xx_recalc_rate
ffff8000809a0a48 t samsung_pll531x_recalc_rate
ffff8000809a0ab0 t samsung_pll46xx_recalc_rate
ffff8000809a0bb8 t samsung_pll2550xx_set_rate
ffff8000809a0d08 t samsung_pll0822x_set_rate
ffff8000809a0e70 t samsung_pll2650x_set_rate
ffff8000809a0f90 t samsung_pll2650xx_set_rate
ffff8000809a10b0 t samsung_pll35xx_set_rate
ffff8000809a1288 t samsung_pll0831x_set_rate
ffff8000809a1408 t samsung_pll36xx_set_rate
ffff8000809a15f8 t samsung_pll45xx_set_rate
ffff8000809a17b8 t samsung_pll1031x_set_rate
ffff8000809a1968 t samsung_pll46xx_set_rate
ffff8000809a1c08 t exynos_cpuclk_recalc_rate
ffff8000809a1c28 t exynos_cpuclk_notifier_cb
ffff8000809a1ce8 t exynos850_alt_parent_set_max_rate
ffff8000809a1dc8 t exynos_cpuclk_determine_rate
ffff8000809a1e28 t wait_until_divider_stable
ffff8000809a1ee8 t exynos_set_safe_div.isra.0
ffff8000809a1f88 t wait_until_mux_stable
ffff8000809a2068 t exynos5433_cpuclk_post_rate_change
ffff8000809a2138 t exynos_cpuclk_post_rate_change
ffff8000809a2288 t exynos850_cpuclk_post_rate_change
ffff8000809a23c8 t exynos5433_cpuclk_pre_rate_change
ffff8000809a25a8 t exynos850_cpuclk_pre_rate_change
ffff8000809a27b8 t exynos_cpuclk_pre_rate_change
ffff8000809a2a48 t exynos_clkout_suspend
ffff8000809a2a90 t exynos_clkout_resume
ffff8000809a2ac8 t exynos_clkout_remove
ffff8000809a2b28 t exynos_clkout_probe
ffff8000809a2ea8 T exynos_arm64_cmu_suspend
ffff8000809a2fd0 T exynos_arm64_cmu_resume
ffff8000809a3108 T ccu_pll_notifier_register
ffff8000809a3158 t devm_sunxi_ccu_release
ffff8000809a31f0 t sunxi_ccu_probe
ffff8000809a34b0 T devm_sunxi_ccu_probe
ffff8000809a35a8 t ccu_helper_wait_for_lock.part.0
ffff8000809a3688 T ccu_helper_wait_for_lock
ffff8000809a36e8 t ccu_pll_notifier_cb
ffff8000809a3790 T ccu_is_better_rate
ffff8000809a3888 T of_sunxi_ccu_probe
ffff8000809a3948 T sunxi_ccu_set_mmc_timing_mode
ffff8000809a3a10 T sunxi_ccu_get_mmc_timing_mode
ffff8000809a3a88 t ccu_reset_assert
ffff8000809a3b48 t ccu_reset_status
ffff8000809a3ba8 t ccu_reset_deassert
ffff8000809a3c68 t ccu_reset_reset
ffff8000809a3ce8 t ccu_div_set_rate
ffff8000809a3e08 t ccu_div_get_parent
ffff8000809a3e48 t ccu_div_set_parent
ffff8000809a3e90 t ccu_div_determine_rate
ffff8000809a3ef0 t ccu_div_round_rate
ffff8000809a3f88 t ccu_div_is_enabled
ffff8000809a3fc8 t ccu_div_disable
ffff8000809a4010 t ccu_div_enable
ffff8000809a4050 t ccu_div_recalc_rate
ffff8000809a4148 T ccu_frac_helper_has_rate
ffff8000809a41a8 T ccu_frac_helper_read_rate
ffff8000809a4328 T ccu_frac_helper_set_rate
ffff8000809a4448 T ccu_frac_helper_is_enabled
ffff8000809a44a8 T ccu_frac_helper_disable
ffff8000809a4588 T ccu_frac_helper_enable
ffff8000809a4688 t ccu_gate_recalc_rate
ffff8000809a46b8 t ccu_gate_set_rate
ffff8000809a46d0 t ccu_gate_determine_rate
ffff8000809a47a8 t ccu_gate_is_enabled
ffff8000809a4808 t ccu_gate_helper_enable.part.0
ffff8000809a48b8 T ccu_gate_helper_enable
ffff8000809a4910 t ccu_gate_enable
ffff8000809a4970 t ccu_gate_helper_disable.part.0
ffff8000809a4a28 T ccu_gate_helper_disable
ffff8000809a4a88 t ccu_gate_disable
ffff8000809a4ae8 T ccu_gate_helper_is_enabled
ffff8000809a4b68 t ccu_mux_is_enabled
ffff8000809a4ba8 t ccu_mux_disable
ffff8000809a4bf0 t ccu_mux_enable
ffff8000809a4c30 T ccu_mux_notifier_register
ffff8000809a4c78 t ccu_mux_get_prediv
ffff8000809a4de8 T ccu_mux_helper_apply_prediv
ffff8000809a4e38 t ccu_mux_recalc_rate
ffff8000809a4e98 T ccu_mux_helper_determine_rate
ffff8000809a50d8 t ccu_mux_determine_rate
ffff8000809a5148 T ccu_mux_helper_get_parent
ffff8000809a5248 t ccu_mux_get_parent
ffff8000809a5288 T ccu_mux_helper_set_parent
ffff8000809a5390 t ccu_mux_set_parent
ffff8000809a53e8 t ccu_mux_notifier_cb
ffff8000809a54e8 t ccu_mult_round_rate
ffff8000809a5558 t ccu_mult_set_rate
ffff8000809a5728 t ccu_mult_get_parent
ffff8000809a5768 t ccu_mult_set_parent
ffff8000809a57b0 t ccu_mult_determine_rate
ffff8000809a5810 t ccu_mult_is_enabled
ffff8000809a5850 t ccu_mult_disable
ffff8000809a5898 t ccu_mult_enable
ffff8000809a58d8 t ccu_mult_recalc_rate
ffff8000809a59e8 t ccu_phase_set_phase
ffff8000809a5b28 t ccu_phase_get_phase
ffff8000809a5c28 T ccu_sdm_helper_get_factors
ffff8000809a5cd8 T ccu_sdm_helper_has_rate
ffff8000809a5d48 T ccu_sdm_helper_is_enabled
ffff8000809a5de8 T ccu_sdm_helper_read_rate
ffff8000809a5f68 T ccu_sdm_helper_enable
ffff8000809a60f8 T ccu_sdm_helper_disable
ffff8000809a6228 t ccu_nk_set_rate
ffff8000809a6458 t ccu_nk_is_enabled
ffff8000809a6498 t ccu_nk_disable
ffff8000809a64e8 t ccu_nk_enable
ffff8000809a6528 t ccu_nk_determine_rate
ffff8000809a6668 t ccu_nk_recalc_rate
ffff8000809a6728 t ccu_nkm_get_parent
ffff8000809a6768 t ccu_nkm_set_parent
ffff8000809a67b0 t ccu_nkm_determine_rate
ffff8000809a6810 t ccu_nkm_is_enabled
ffff8000809a6850 t ccu_nkm_disable
ffff8000809a6898 t ccu_nkm_enable
ffff8000809a68d8 t ccu_nkm_find_best.constprop.0
ffff8000809a6a68 t ccu_nkm_set_rate
ffff8000809a6cc8 t ccu_nkm_round_rate
ffff8000809a6ff8 t ccu_nkm_recalc_rate
ffff8000809a70e8 t ccu_nkmp_is_enabled
ffff8000809a7128 t ccu_nkmp_disable
ffff8000809a7170 t ccu_nkmp_enable
ffff8000809a71b0 t ccu_nkmp_set_rate
ffff8000809a75b8 t ccu_nkmp_recalc_rate
ffff8000809a76c8 t ccu_nkmp_determine_rate
ffff8000809a7988 t ccu_nm_determine_rate
ffff8000809a7c18 t ccu_nm_is_enabled
ffff8000809a7c58 t ccu_nm_disable
ffff8000809a7ca8 t ccu_nm_enable
ffff8000809a7ce8 t ccu_nm_recalc_rate
ffff8000809a7e88 t ccu_nm_set_rate
ffff8000809a8268 t ccu_mp_get_parent
ffff8000809a82a8 t ccu_mp_set_parent
ffff8000809a82f0 t ccu_mp_determine_rate
ffff8000809a8350 t ccu_mp_round_rate
ffff8000809a8730 t ccu_mp_is_enabled
ffff8000809a8770 t ccu_mp_disable
ffff8000809a87b8 t ccu_mp_enable
ffff8000809a87f8 t ccu_mp_set_rate
ffff8000809a8a90 t ccu_mp_mmc_set_rate
ffff8000809a8b08 t ccu_mp_mmc_determine_rate
ffff8000809a8c08 t ccu_mp_recalc_rate
ffff8000809a8cf8 t ccu_mp_mmc_recalc_rate
ffff8000809a8d88 t sun50i_a64_ccu_probe
ffff8000809a8ea8 t sun50i_a100_ccu_probe
ffff8000809a90c8 t sun50i_a100_r_ccu_probe
ffff8000809a9148 t sun50i_h6_ccu_probe
ffff8000809a93c8 t sun50i_h6_r_ccu_probe
ffff8000809a9468 t sun50i_h616_ccu_probe
ffff8000809a96a8 t sun55i_a523_ccu_probe
ffff8000809a9788 t sun55i_a523_mcu_ccu_probe
ffff8000809a9828 t sun55i_a523_r_ccu_probe
ffff8000809a98a8 t ccu_iosc_recalc_accuracy
ffff8000809a98c8 t ccu_iosc_is_enabled
ffff8000809a9908 t ccu_iosc_disable
ffff8000809a9950 t ccu_iosc_enable
ffff8000809a9990 t ccu_iosc_32k_recalc_rate
ffff8000809a9a10 t ccu_iosc_32k_prepare
ffff8000809a9a70 t ccu_iosc_32k_unprepare
ffff8000809a9ae8 t ccu_iosc_recalc_rate
ffff8000809a9b48 t ccu_iosc_32k_recalc_accuracy
ffff8000809a9ba8 T sun6i_rtc_ccu_probe
ffff8000809a9d28 t sun8i_h3_ccu_probe
ffff8000809a9e48 t sunxi_de2_clk_probe
ffff8000809aa148 t sun8i_r_ccu_probe
ffff8000809aa1e8 t tegra_clk_rst_deassert
ffff8000809aa2c8 t tegra_clk_rst_assert
ffff8000809aa3a8 t tegra_clk_rst_reset
ffff8000809aa408 T get_reg_bank
ffff8000809aa468 T tegra_clk_set_pllp_out_cpu
ffff8000809aa4b8 T tegra_clk_periph_suspend
ffff8000809aa558 T tegra_clk_periph_resume
ffff8000809aa688 T tegra_init_from_table
ffff8000809aa858 T tegra_register_devclks
ffff8000809aa958 T tegra_clk_dev_register
ffff8000809aab08 t clk_sync_source_recalc_rate
ffff8000809aab28 t clk_sync_source_determine_rate
ffff8000809aab68 t clk_sync_source_set_rate
ffff8000809aab88 T tegra_clk_register_sync_source
ffff8000809aaca0 t pm_runtime_put
ffff8000809aacd0 t pm_runtime_resume_and_get
ffff8000809aad88 t tegra_clock_set_pd_state.isra.0
ffff8000809aae88 t tegra_clock_probe
ffff8000809ab048 t tegra_clock_change_notify
ffff8000809ab148 t dfll_clk_is_enabled
ffff8000809ab168 t dfll_clk_recalc_rate
ffff8000809ab188 t attr_enable_get
ffff8000809ab1b8 t attr_lock_get
ffff8000809ab1e8 T tegra_dfll_runtime_resume
ffff8000809ab2d0 T tegra_dfll_runtime_suspend
ffff8000809ab328 T tegra_dfll_suspend
ffff8000809ab3a8 t dfll_calculate_rate_request
ffff8000809ab5c8 t dfll_clk_determine_rate
ffff8000809ab650 t find_vdd_map_entry_exact
ffff8000809ab768 t attr_registers_open
ffff8000809ab7b8 t rate_fops_open
ffff8000809ab818 t lock_fops_open
ffff8000809ab878 t enable_fops_open
ffff8000809ab8d8 T tegra_dfll_unregister
ffff8000809ab9a8 t attr_registers_show
ffff8000809abb88 t dfll_tune_low
ffff8000809abc18 t dfll_set_default_params.constprop.0
ffff8000809abcd0 t dfll_enable
ffff8000809abd68 t dfll_disable
ffff8000809abdf8 t attr_enable_set
ffff8000809abe50 t dfll_set_frequency_request.isra.0
ffff8000809abec8 t dfll_clk_set_rate
ffff8000809ac008 t attr_rate_set
ffff8000809ac130 t attr_rate_get
ffff8000809ac1a8 t dfll_unlock
ffff8000809ac318 t dfll_clk_disable
ffff8000809ac388 t dfll_lock
ffff8000809ac530 t dfll_clk_enable
ffff8000809ac5c8 t attr_lock_set
ffff8000809ac628 t dfll_init_out_if
ffff8000809ac850 T tegra_dfll_resume
ffff8000809ac928 T tegra_dfll_register
ffff8000809ad9c8 t clk_frac_div_determine_rate
ffff8000809adab8 t clk_frac_div_set_rate
ffff8000809adbc8 t clk_divider_restore_context
ffff8000809adc38 t clk_frac_div_recalc_rate
ffff8000809adcb8 T tegra_clk_register_divider
ffff8000809ade28 T tegra_clk_register_mc
ffff8000809adec8 t clk_periph_get_parent
ffff8000809adf28 t clk_periph_set_parent
ffff8000809adf88 t clk_periph_recalc_rate
ffff8000809adfe8 t clk_periph_determine_rate
ffff8000809ae048 t clk_periph_set_rate
ffff8000809ae0a8 t clk_periph_is_enabled
ffff8000809ae108 t clk_periph_enable
ffff8000809ae168 t clk_periph_disable
ffff8000809ae1b0 t clk_periph_disable_unused
ffff8000809ae1f8 t clk_periph_restore_context
ffff8000809ae2b8 T tegra_clk_register_periph
ffff8000809ae470 T tegra_clk_register_periph_nodiv
ffff8000809ae5b0 T tegra_clk_register_periph_data
ffff8000809ae768 t tegra_clk_periph_fixed_enable
ffff8000809ae7a8 t tegra_clk_periph_fixed_disable
ffff8000809ae7e8 t tegra_clk_periph_fixed_recalc_rate
ffff8000809ae810 t tegra_clk_periph_fixed_is_enabled
ffff8000809ae8a8 T tegra_clk_register_periph_fixed
ffff8000809aea28 t clk_periph_disable
ffff8000809aeb30 t clk_periph_enable
ffff8000809aec50 t clk_periph_disable_unused
ffff8000809aed30 t clk_periph_is_enabled
ffff8000809aedc8 T tegra_clk_register_periph_gate
ffff8000809aef88 t _calc_rate
ffff8000809af268 t _tegra_clk_register_pll
ffff8000809af398 t _get_table_rate
ffff8000809af498 t clk_pll_determine_rate
ffff8000809af5a8 t clk_pllre_determine_rate
ffff8000809af670 t clk_pll_wait_for_lock
ffff8000809af770 t _calc_dynamic_ramp_rate
ffff8000809af8b0 t _pll_ramp_calc_pll
ffff8000809af9a8 t clk_pll_ramp_determine_rate
ffff8000809afad8 t clk_plle_tegra210_is_enabled
ffff8000809afb08 t _pllcx_update_dynamic_coef
ffff8000809afc28 t clk_plle_recalc_rate
ffff8000809afcd8 t _clk_plle_tegra_init_parent.isra.0
ffff8000809afdc8 t tegra_clk_plle_t210_restore_context
ffff8000809afe10 t clk_pll_is_enabled
ffff8000809afe70 t clk_plle_tegra210_disable
ffff8000809aff48 t _clk_pll_disable
ffff8000809b0068 t clk_pll_disable
ffff8000809b0110 t clk_plle_tegra114_disable
ffff8000809b01b0 t clk_pllc_disable
ffff8000809b0250 t _clk_pll_enable
ffff8000809b03d8 t clk_pllc_enable
ffff8000809b0508 t clk_pllu_enable
ffff8000809b0768 t clk_pllu_tegra114_enable
ffff8000809b0a38 t clk_pll_enable
ffff8000809b0b30 t clk_plle_tegra114_enable
ffff8000809b0ea8 t _update_pll_mnp
ffff8000809b10f8 t clk_plle_tegra210_enable
ffff8000809b13c8 t _get_pll_mnp
ffff8000809b15d8 t clk_pllre_recalc_rate
ffff8000809b1668 t clk_pllre_set_rate
ffff8000809b1808 t _program_pll
ffff8000809b1a90 t clk_pll_set_rate
ffff8000809b1c90 t tegra_clk_pll_restore_context
ffff8000809b1d70 t clk_pllxc_set_rate
ffff8000809b1ea8 t clk_pllc_set_rate
ffff8000809b2068 t clk_pll_recalc_rate
ffff8000809b2248 t clk_plle_enable
ffff8000809b2590 T tegra_pll_wait_for_lock
ffff8000809b25c8 T tegra_pll_p_div_to_hw
ffff8000809b2628 T tegra_pll_get_fixed_mdiv
ffff8000809b2690 T tegra_clk_register_pll
ffff8000809b27b0 T tegra_clk_register_plle
ffff8000809b28f0 T tegra_clk_register_pllu
ffff8000809b2a08 T tegra_clk_register_pllxc
ffff8000809b2c90 T tegra_clk_register_pllre
ffff8000809b2ea8 T tegra_clk_register_pllm
ffff8000809b3050 T tegra_clk_register_pllc
ffff8000809b3350 T tegra_clk_register_plle_tegra114
ffff8000809b3468 T tegra_clk_register_pllu_tegra114
ffff8000809b3578 T tegra_clk_register_pllss
ffff8000809b38a8 T tegra_clk_register_pllre_tegra210
ffff8000809b39f0 T tegra_clk_register_plle_tegra210
ffff8000809b3b08 T tegra_clk_register_pllc_tegra210
ffff8000809b3ca8 T tegra_clk_register_pllss_tegra210
ffff8000809b3e78 T tegra_clk_register_pllmb
ffff8000809b41a8 t clk_pll_out_disable
ffff8000809b4250 t clk_pll_out_is_enabled
ffff8000809b4290 t clk_pll_out_enable
ffff8000809b4338 t tegra_clk_pll_out_restore_context
ffff8000809b43b0 T tegra_clk_register_pll_out
ffff8000809b4528 t clk_sdmmc_mux_is_enabled
ffff8000809b4588 t clk_sdmmc_mux_enable
ffff8000809b45e8 t clk_sdmmc_mux_disable
ffff8000809b4630 t clk_sdmmc_mux_disable_unused
ffff8000809b4678 t clk_sdmmc_mux_determine_rate
ffff8000809b4778 t clk_sdmmc_mux_get_parent
ffff8000809b4850 t clk_sdmmc_mux_set_rate
ffff8000809b4948 t clk_sdmmc_mux_recalc_rate
ffff8000809b4988 t clk_sdmmc_mux_set_parent
ffff8000809b49e8 t clk_sdmmc_mux_restore_context
ffff8000809b4aa8 T tegra_clk_register_sdmmc_mux_div
ffff8000809b4c48 t clk_super_determine_rate
ffff8000809b4ca8 t clk_super_recalc_rate
ffff8000809b4d08 t clk_super_set_rate
ffff8000809b4d68 t clk_super_get_parent
ffff8000809b4e08 t clk_super_set_parent
ffff8000809b4fb8 t clk_super_restore_context
ffff8000809b5058 t clk_super_mux_restore_context
ffff8000809b50d8 T tegra_clk_register_super_mux
ffff8000809b5238 T tegra_clk_register_super_clk
ffff8000809b53a8 T tegra_clk_osc_resume
ffff8000809b5448 t cclk_super_get_parent
ffff8000809b5488 t cclk_super_set_parent
ffff8000809b54d0 t cclk_super_set_rate
ffff8000809b5518 t cclk_super_determine_rate
ffff8000809b5678 t cclk_super_recalc_rate
ffff8000809b5730 T tegra_clk_register_super_cclk
ffff8000809b58e8 T tegra_cclk_pre_pllx_rate_change
ffff8000809b59b0 T tegra_cclk_post_pllx_rate_change
ffff8000809b5a48 t tegra124_dfll_fcpu_remove
ffff8000809b5aa8 t tegra124_dfll_fcpu_probe
ffff8000809b5d48 t tegra124_disable_cpu_clock
ffff8000809b5d68 t tegra124_cpu_clock_resume
ffff8000809b5dd0 t tegra124_clk_src_onecell_get
ffff8000809b5e38 t tegra124_wait_cpu_in_reset
ffff8000809b5e98 t tegra124_reset_assert
ffff8000809b5ee8 t tegra124_reset_deassert
ffff8000809b5f38 t tegra124_cpu_clock_suspend
ffff8000809b6008 T tegra_cvb_add_opp_table
ffff8000809b6308 T tegra_cvb_remove_opp_table
ffff8000809b63a0 t readl
ffff8000809b63c8 T tegra210_clk_emc_dll_enable
ffff8000809b6408 T tegra210_clk_emc_dll_update_setting
ffff8000809b6430 T tegra210_clk_emc_update_setting
ffff8000809b6458 t tegra210_clk_pll_set_gain
ffff8000809b64b0 t tegra210_clk_adjust_vco_min
ffff8000809b64e8 t tegra210_disable_cpu_clock
ffff8000809b6508 t tegra210_cpu_clock_resume
ffff8000809b6548 t tegra210_pll_fixed_mdiv_cfg
ffff8000809b6748 t pll_qlin_p_to_pdiv
ffff8000809b67c8 t pll_expo_p_to_pdiv
ffff8000809b6868 t tegra210_wait_cpu_in_reset
ffff8000809b68c8 T tegra210_xusb_pll_hw_sequence_start
ffff8000809b6908 T tegra210_sata_pll_hw_sequence_start
ffff8000809b6948 T tegra210_put_utmipll_out_iddq
ffff8000809b6988 T tegra210_plle_hw_sequence_is_enabled
ffff8000809b69b0 T tegra210_xusb_pll_hw_control_enable
ffff8000809b69f8 T tegra210_sata_pll_hw_control_enable
ffff8000809b6a38 T tegra210_set_sata_pll_seq_sw
ffff8000809b6a88 T tegra210_put_utmipll_in_iddq
ffff8000809b6b08 t tegra210_cpu_clock_suspend
ffff8000809b6b60 t _pll_misc_chk_default
ffff8000809b6c28 t tegra210_plla_set_defaults
ffff8000809b6d88 t tegra210_clk_suspend
ffff8000809b6e28 t tegra210_generic_mbist_war
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ffff8000809b7150 t tegra210_disp_mbist_war
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ffff8000809c4ee8 T mtk_infracfg_set_bus_protection
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ffff8000810e1690 d __compound_literal.15
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ffff8000810e1710 d tdmb_dout3_pins
ffff8000810e1718 d tdmb_din3_pins
ffff8000810e1720 d tdmb_dout2_pins
ffff8000810e1728 d tdmb_din2_pins
ffff8000810e1730 d tdmb_dout1_pins
ffff8000810e1738 d tdmb_din1_pins
ffff8000810e1740 d tdmb_dout0_pins
ffff8000810e1748 d tdmb_din0_pins
ffff8000810e1750 d tdmb_fs_slv_pins
ffff8000810e1758 d tdmb_fs_pins
ffff8000810e1760 d tdmb_sclk_slv_pins
ffff8000810e1768 d tdmb_sclk_pins
ffff8000810e1770 d tdmc_dout3_pins
ffff8000810e1778 d tdmc_din3_pins
ffff8000810e1780 d tdmc_dout2_pins
ffff8000810e1788 d tdmc_din2_pins
ffff8000810e1790 d tdmc_dout1_pins
ffff8000810e1798 d tdmc_din1_pins
ffff8000810e17a0 d tdmc_dout0_pins
ffff8000810e17a8 d tdmc_din0_pins
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ffff8000810e17c8 d tdmc_sclk_pins
ffff8000810e17d0 d tdma_din1_pins
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ffff8000810e17e0 d tdma_dout0_x15_pins
ffff8000810e17e8 d tdma_dout0_x14_pins
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ffff8000810e1800 d tdma_fs_pins
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ffff8000810e1810 d tdma_sclk_pins
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ffff8000810e1820 d mclk_c_pins
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ffff8000810e1830 d pdm_din2_pins
ffff8000810e1838 d pdm_din1_pins
ffff8000810e1840 d pdm_din0_pins
ffff8000810e1848 d pdm_dclk_a19_pins
ffff8000810e1850 d pdm_dclk_a14_pins
ffff8000810e1858 d eth_txd3_rgmii_pins
ffff8000810e1860 d eth_txd2_rgmii_pins
ffff8000810e1868 d eth_rgmii_tx_clk_pins
ffff8000810e1870 d eth_rxd3_rgmii_pins
ffff8000810e1878 d eth_rxd2_rgmii_pins
ffff8000810e1880 d eth_mdc_y_pins
ffff8000810e1888 d eth_mdio_y_pins
ffff8000810e1890 d eth_rx_dv_y_pins
ffff8000810e1898 d eth_rxd1_y_pins
ffff8000810e18a0 d eth_rxd0_y_pins
ffff8000810e18a8 d eth_rgmii_rx_clk_y_pins
ffff8000810e18b0 d eth_txen_y_pins
ffff8000810e18b8 d eth_txd1_y_pins
ffff8000810e18c0 d eth_txd0_y_pins
ffff8000810e18c8 d eth_mdc_x_pins
ffff8000810e18d0 d eth_mdio_x_pins
ffff8000810e18d8 d eth_rx_dv_x_pins
ffff8000810e18e0 d eth_rxd1_x_pins
ffff8000810e18e8 d eth_rxd0_x_pins
ffff8000810e18f0 d eth_rgmii_rx_clk_x_pins
ffff8000810e18f8 d eth_txen_x_pins
ffff8000810e1900 d eth_txd1_x_pins
ffff8000810e1908 d eth_txd0_x_pins
ffff8000810e1910 d jtag_tms_x_pins
ffff8000810e1918 d jtag_clk_x_pins
ffff8000810e1920 d jtag_tdi_x_pins
ffff8000810e1928 d jtag_tdo_x_pins
ffff8000810e1930 d spdif_out_a20_pins
ffff8000810e1938 d spdif_out_a19_pins
ffff8000810e1940 d spdif_out_a11_pins
ffff8000810e1948 d spdif_out_a1_pins
ffff8000810e1950 d spdif_out_z_pins
ffff8000810e1958 d spdif_in_a20_pins
ffff8000810e1960 d spdif_in_a19_pins
ffff8000810e1968 d spdif_in_a7_pins
ffff8000810e1970 d spdif_in_a1_pins
ffff8000810e1978 d spdif_in_z_pins
ffff8000810e1980 d pwm_vs_pins
ffff8000810e1988 d pwm_d_x16_pins
ffff8000810e1990 d pwm_d_x11_pins
ffff8000810e1998 d pwm_c_a_pins
ffff8000810e19a0 d pwm_c_x17_pins
ffff8000810e19a8 d pwm_c_x10_pins
ffff8000810e19b0 d pwm_b_a_pins
ffff8000810e19b8 d pwm_b_x_pins
ffff8000810e19c0 d pwm_b_z_pins
ffff8000810e19c8 d pwm_a_a_pins
ffff8000810e19d0 d pwm_a_x20_pins
ffff8000810e19d8 d pwm_a_x18_pins
ffff8000810e19e0 d pwm_a_z_pins
ffff8000810e19e8 d uart_ao_rts_b_z_pins
ffff8000810e19f0 d uart_ao_cts_b_z_pins
ffff8000810e19f8 d uart_ao_rx_b_z_pins
ffff8000810e1a00 d uart_ao_tx_b_z_pins
ffff8000810e1a08 d uart_rx_b_x_pins
ffff8000810e1a10 d uart_tx_b_x_pins
ffff8000810e1a18 d uart_cts_b_x_pins
ffff8000810e1a20 d uart_rts_b_x_pins
ffff8000810e1a28 d uart_rx_b_z_pins
ffff8000810e1a30 d uart_tx_b_z_pins
ffff8000810e1a38 d uart_cts_b_z_pins
ffff8000810e1a40 d uart_rts_b_z_pins
ffff8000810e1a48 d uart_rx_a_pins
ffff8000810e1a50 d uart_tx_a_pins
ffff8000810e1a58 d uart_cts_a_pins
ffff8000810e1a60 d uart_rts_a_pins
ffff8000810e1a68 d i2c3_sck_a20_pins
ffff8000810e1a70 d i2c3_sda_a19_pins
ffff8000810e1a78 d i2c3_sck_a13_pins
ffff8000810e1a80 d i2c3_sda_a12_pins
ffff8000810e1a88 d i2c3_sck_a7_pins
ffff8000810e1a90 d i2c3_sda_a6_pins
ffff8000810e1a98 d i2c2_sck_a_pins
ffff8000810e1aa0 d i2c2_sda_a_pins
ffff8000810e1aa8 d i2c2_sda_x_pins
ffff8000810e1ab0 d i2c2_sck_x_pins
ffff8000810e1ab8 d i2c1_sda_x_pins
ffff8000810e1ac0 d i2c1_sck_x_pins
ffff8000810e1ac8 d i2c1_sda_z_pins
ffff8000810e1ad0 d i2c1_sck_z_pins
ffff8000810e1ad8 d i2c0_sda_pins
ffff8000810e1ae0 d i2c0_sck_pins
ffff8000810e1ae8 d spi1_ss1_pins
ffff8000810e1af0 d spi1_ss0_a_pins
ffff8000810e1af8 d spi1_miso_a_pins
ffff8000810e1b00 d spi1_mosi_a_pins
ffff8000810e1b08 d spi1_clk_a_pins
ffff8000810e1b10 d spi1_ss0_x_pins
ffff8000810e1b18 d spi1_miso_x_pins
ffff8000810e1b20 d spi1_mosi_x_pins
ffff8000810e1b28 d spi1_clk_x_pins
ffff8000810e1b30 d spi0_ss2_pins
ffff8000810e1b38 d spi0_ss1_pins
ffff8000810e1b40 d spi0_ss0_pins
ffff8000810e1b48 d spi0_miso_pins
ffff8000810e1b50 d spi0_mosi_pins
ffff8000810e1b58 d spi0_clk_pins
ffff8000810e1b60 d sdio_cmd_pins
ffff8000810e1b68 d sdio_clk_pins
ffff8000810e1b70 d sdio_d3_pins
ffff8000810e1b78 d sdio_d2_pins
ffff8000810e1b80 d sdio_d1_pins
ffff8000810e1b88 d sdio_d0_pins
ffff8000810e1b90 d nor_cs_pins
ffff8000810e1b98 d nor_wp_pins
ffff8000810e1ba0 d nor_c_pins
ffff8000810e1ba8 d nor_q_pins
ffff8000810e1bb0 d nor_d_pins
ffff8000810e1bb8 d nor_hold_pins
ffff8000810e1bc0 d nand_rb0_pins
ffff8000810e1bc8 d nand_ren_wr_pins
ffff8000810e1bd0 d nand_wen_clk_pins
ffff8000810e1bd8 d nand_cle_pins
ffff8000810e1be0 d nand_ale_pins
ffff8000810e1be8 d nand_ce0_pins
ffff8000810e1bf0 d emmc_ds_pins
ffff8000810e1bf8 d emmc_cmd_pins
ffff8000810e1c00 d emmc_clk_pins
ffff8000810e1c08 d emmc_nand_d7_pins
ffff8000810e1c10 d emmc_nand_d6_pins
ffff8000810e1c18 d emmc_nand_d5_pins
ffff8000810e1c20 d emmc_nand_d4_pins
ffff8000810e1c28 d emmc_nand_d3_pins
ffff8000810e1c30 d emmc_nand_d2_pins
ffff8000810e1c38 d emmc_nand_d1_pins
ffff8000810e1c40 d emmc_nand_d0_pins
ffff8000810e1c48 d meson_axg_aobus_pins
ffff8000810e1db0 d meson_axg_periphs_pins
ffff8000810e25c0 d meson_g12a_pinctrl_dt_match
ffff8000810e2818 d meson_g12a_aobus_pinctrl_data
ffff8000810e2870 d meson_g12a_periphs_pinctrl_data
ffff8000810e28c8 d meson_g12a_aobus_pmx_banks_data
ffff8000810e28d8 d meson_g12a_aobus_pmx_banks
ffff8000810e2908 d meson_g12a_periphs_pmx_banks_data
ffff8000810e2918 d meson_g12a_periphs_pmx_banks
ffff8000810e29a8 d meson_g12a_aobus_banks
ffff8000810e2a38 d meson_g12a_periphs_banks
ffff8000810e2be8 d meson_g12a_aobus_functions
ffff8000810e2db0 d meson_g12a_periphs_functions
ffff8000810e3170 d mclk0_ao_groups
ffff8000810e3178 d tdm_ao_b_groups
ffff8000810e31c8 d spdif_ao_out_groups
ffff8000810e31d0 d tsin_ao_a_groups
ffff8000810e31f0 d cec_ao_b_groups
ffff8000810e31f8 d cec_ao_a_groups
ffff8000810e3200 d jtag_a_groups
ffff8000810e3220 d pwm_ao_d_groups
ffff8000810e3238 d pwm_ao_c_groups
ffff8000810e3250 d pwm_ao_b_groups
ffff8000810e3258 d pwm_ao_a_groups
ffff8000810e3268 d pwm_a_e_groups
ffff8000810e3270 d remote_ao_out_groups
ffff8000810e3278 d remote_ao_input_groups
ffff8000810e3280 d i2c_ao_slave_groups
ffff8000810e3290 d i2c_ao_groups
ffff8000810e32b0 d uart_ao_b_groups
ffff8000810e32e0 d uart_ao_a_groups
ffff8000810e3300 d gpio_aobus_groups
ffff8000810e3378 d pcie_clkreqn_groups
ffff8000810e3380 d tdm_c_groups
ffff8000810e3440 d tdm_b_groups
ffff8000810e34b0 d tdm_a_groups
ffff8000810e34f0 d mclk1_groups
ffff8000810e3508 d mclk0_groups
ffff8000810e3510 d spdif_out_groups
ffff8000810e3528 d spdif_in_groups
ffff8000810e3540 d pdm_groups
ffff8000810e35e0 d hdmitx_groups
ffff8000810e35f8 d tsin_b_groups
ffff8000810e3678 d tsin_a_groups
ffff8000810e3698 d bt565_a_groups
ffff8000810e36f0 d jtag_b_groups
ffff8000810e3710 d cec_ao_b_h_groups
ffff8000810e3718 d cec_ao_a_h_groups
ffff8000810e3720 d pwm_f_groups
ffff8000810e3740 d pwm_e_groups
ffff8000810e3748 d pwm_d_groups
ffff8000810e3768 d pwm_c_groups
ffff8000810e3788 d pwm_b_groups
ffff8000810e37b0 d pwm_a_groups
ffff8000810e37b8 d eth_groups
ffff8000810e3838 d iso7816_groups
ffff8000810e3878 d uart_ao_a_c_groups
ffff8000810e3888 d uart_c_groups
ffff8000810e38a8 d uart_b_groups
ffff8000810e38b8 d uart_a_groups
ffff8000810e38d8 d i2c3_groups
ffff8000810e38f8 d i2c2_groups
ffff8000810e3918 d i2c1_groups
ffff8000810e3948 d i2c0_groups
ffff8000810e3978 d spi1_groups
ffff8000810e3998 d spi0_groups
ffff8000810e39d8 d sdcard_groups
ffff8000810e3a38 d sdio_groups
ffff8000810e3a70 d nor_groups
ffff8000810e3aa0 d nand_groups
ffff8000810e3b20 d emmc_groups
ffff8000810e3b78 d gpio_periphs_groups
ffff8000810e3e20 d meson_g12a_aobus_groups
ffff8000810e4640 d __compound_literal.499
ffff8000810e4648 d __compound_literal.498
ffff8000810e4650 d __compound_literal.497
ffff8000810e4658 d __compound_literal.496
ffff8000810e4660 d __compound_literal.495
ffff8000810e4668 d __compound_literal.494
ffff8000810e4670 d __compound_literal.493
ffff8000810e4678 d __compound_literal.492
ffff8000810e4680 d __compound_literal.491
ffff8000810e4688 d __compound_literal.490
ffff8000810e4690 d __compound_literal.489
ffff8000810e4698 d __compound_literal.488
ffff8000810e46a0 d __compound_literal.487
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ffff8000810e46b0 d __compound_literal.485
ffff8000810e46b8 d __compound_literal.484
ffff8000810e46c0 d __compound_literal.483
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ffff8000810e46d0 d __compound_literal.481
ffff8000810e46d8 d __compound_literal.480
ffff8000810e46e0 d __compound_literal.479
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ffff8000810e46f0 d __compound_literal.477
ffff8000810e46f8 d __compound_literal.476
ffff8000810e4700 d __compound_literal.475
ffff8000810e4708 d __compound_literal.474
ffff8000810e4710 d __compound_literal.473
ffff8000810e4718 d __compound_literal.472
ffff8000810e4720 d __compound_literal.471
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ffff8000810e4738 d __compound_literal.468
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ffff8000810e4748 d __compound_literal.466
ffff8000810e4750 d __compound_literal.465
ffff8000810e4758 d __compound_literal.464
ffff8000810e4760 d __compound_literal.463
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ffff8000810e4778 d __compound_literal.460
ffff8000810e4780 d __compound_literal.459
ffff8000810e4788 d __compound_literal.458
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ffff8000810e4858 d __compound_literal.432
ffff8000810e4860 d __compound_literal.431
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ffff8000810e4870 d __compound_literal.429
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ffff8000810e4888 d __compound_literal.426
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ffff8000810e48a8 d __compound_literal.422
ffff8000810e48b0 d __compound_literal.421
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ffff8000810e48c0 d mclk0_ao_pins
ffff8000810e48c8 d tdm_ao_b_dout2_pins
ffff8000810e48d0 d tdm_ao_b_dout1_pins
ffff8000810e48d8 d tdm_ao_b_dout0_pins
ffff8000810e48e0 d tdm_ao_b_din2_pins
ffff8000810e48e8 d tdm_ao_b_din1_pins
ffff8000810e48f0 d tdm_ao_b_din0_pins
ffff8000810e48f8 d tdm_ao_b_sclk_pins
ffff8000810e4900 d tdm_ao_b_fs_pins
ffff8000810e4908 d tdm_ao_b_slv_sclk_pins
ffff8000810e4910 d tdm_ao_b_slv_fs_pins
ffff8000810e4918 d spdif_ao_out_pins
ffff8000810e4920 d tsin_ao_a_valid_pins
ffff8000810e4928 d tsin_ao_aclk_pins
ffff8000810e4930 d tsin_ao_adin0_pins
ffff8000810e4938 d tsin_ao_asop_pins
ffff8000810e4940 d cec_ao_b_pins
ffff8000810e4948 d cec_ao_a_pins
ffff8000810e4950 d jtag_a_tms_pins
ffff8000810e4958 d jtag_a_clk_pins
ffff8000810e4960 d jtag_a_tdo_pins
ffff8000810e4968 d jtag_a_tdi_pins
ffff8000810e4970 d pwm_ao_d_e_pins
ffff8000810e4978 d pwm_ao_d_10_pins
ffff8000810e4980 d pwm_ao_d_5_pins
ffff8000810e4988 d pwm_ao_c_6_pins
ffff8000810e4990 d pwm_ao_c_hiz_pins
ffff8000810e4998 d pwm_ao_c_4_pins
ffff8000810e49a0 d pwm_ao_b_pins
ffff8000810e49a8 d pwm_ao_a_hiz_pins
ffff8000810e49b0 d pwm_ao_a_pins
ffff8000810e49b8 d pwm_a_e_pins
ffff8000810e49c0 d remote_ao_out_pins
ffff8000810e49c8 d remote_ao_input_pins
ffff8000810e49d0 d i2c_ao_slave_sda_pins
ffff8000810e49d8 d i2c_ao_slave_sck_pins
ffff8000810e49e0 d i2c_ao_sda_e_pins
ffff8000810e49e8 d i2c_ao_sck_e_pins
ffff8000810e49f0 d i2c_ao_sda_pins
ffff8000810e49f8 d i2c_ao_sck_pins
ffff8000810e4a00 d uart_ao_b_rts_pins
ffff8000810e4a08 d uart_ao_b_cts_pins
ffff8000810e4a10 d uart_ao_b_rx_9_pins
ffff8000810e4a18 d uart_ao_b_tx_8_pins
ffff8000810e4a20 d uart_ao_b_rx_3_pins
ffff8000810e4a28 d uart_ao_b_tx_2_pins
ffff8000810e4a30 d uart_ao_a_rts_pins
ffff8000810e4a38 d uart_ao_a_cts_pins
ffff8000810e4a40 d uart_ao_a_rx_pins
ffff8000810e4a48 d uart_ao_a_tx_pins
ffff8000810e4a50 d meson_g12a_periphs_groups
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ffff8000810e7438 d __compound_literal.418
ffff8000810e7440 d __compound_literal.417
ffff8000810e7448 d __compound_literal.416
ffff8000810e7450 d __compound_literal.415
ffff8000810e7458 d __compound_literal.414
ffff8000810e7460 d __compound_literal.413
ffff8000810e7468 d __compound_literal.412
ffff8000810e7470 d __compound_literal.411
ffff8000810e7478 d __compound_literal.410
ffff8000810e7480 d __compound_literal.409
ffff8000810e7488 d __compound_literal.408
ffff8000810e7490 d __compound_literal.407
ffff8000810e7498 d __compound_literal.406
ffff8000810e74a0 d __compound_literal.405
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ffff8000810e83e0 d tsin_b_din5_pins
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ffff8000810e83f0 d tsin_b_din3_pins
ffff8000810e83f8 d tsin_b_din2_pins
ffff8000810e8400 d tsin_b_din1_pins
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ffff8000810e8470 d bt565_a_din7_pins
ffff8000810e8478 d bt565_a_din6_pins
ffff8000810e8480 d bt565_a_din5_pins
ffff8000810e8488 d bt565_a_din4_pins
ffff8000810e8490 d bt565_a_din3_pins
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ffff8000810e84c0 d bt565_a_vs_pins
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ffff8000810e85d8 d eth_rxd2_rgmii_pins
ffff8000810e85e0 d eth_rxd1_pins
ffff8000810e85e8 d eth_rxd0_pins
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ffff8000810e8600 d eth_mdc_pins
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ffff8000810e8620 d iso7816_data_h_pins
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ffff8000810e8630 d iso7816_data_x_pins
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ffff8000810e8640 d iso7816_data_c_pins
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ffff8000810e86c0 d i2c3_sck_h_pins
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ffff8000810e86f0 d i2c1_sck_h7_pins
ffff8000810e86f8 d i2c1_sda_h6_pins
ffff8000810e8700 d i2c1_sck_h3_pins
ffff8000810e8708 d i2c1_sda_h2_pins
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ffff8000810e8718 d i2c1_sda_x_pins
ffff8000810e8720 d i2c0_sck_z8_pins
ffff8000810e8728 d i2c0_sda_z7_pins
ffff8000810e8730 d i2c0_sck_z1_pins
ffff8000810e8738 d i2c0_sda_z0_pins
ffff8000810e8740 d i2c0_sck_c_pins
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ffff8000810e8758 d spi1_ss0_pins
ffff8000810e8760 d spi1_miso_pins
ffff8000810e8768 d spi1_mosi_pins
ffff8000810e8770 d spi0_clk_x_pins
ffff8000810e8778 d spi0_ss0_x_pins
ffff8000810e8780 d spi0_miso_x_pins
ffff8000810e8788 d spi0_mosi_x_pins
ffff8000810e8790 d spi0_clk_c_pins
ffff8000810e8798 d spi0_ss0_c_pins
ffff8000810e87a0 d spi0_miso_c_pins
ffff8000810e87a8 d spi0_mosi_c_pins
ffff8000810e87b0 d sdcard_cmd_z_pins
ffff8000810e87b8 d sdcard_clk_z_pins
ffff8000810e87c0 d sdcard_d3_z_pins
ffff8000810e87c8 d sdcard_d2_z_pins
ffff8000810e87d0 d sdcard_d1_z_pins
ffff8000810e87d8 d sdcard_d0_z_pins
ffff8000810e87e0 d sdcard_cmd_c_pins
ffff8000810e87e8 d sdcard_clk_c_pins
ffff8000810e87f0 d sdcard_d3_c_pins
ffff8000810e87f8 d sdcard_d2_c_pins
ffff8000810e8800 d sdcard_d1_c_pins
ffff8000810e8808 d sdcard_d0_c_pins
ffff8000810e8810 d sdio_cmd_pins
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ffff8000810e8820 d sdio_d3_pins
ffff8000810e8828 d sdio_d2_pins
ffff8000810e8830 d sdio_d1_pins
ffff8000810e8838 d sdio_d0_pins
ffff8000810e8840 d nor_cs_pins
ffff8000810e8848 d nor_wp_pins
ffff8000810e8850 d nor_c_pins
ffff8000810e8858 d nor_q_pins
ffff8000810e8860 d nor_d_pins
ffff8000810e8868 d nor_hold_pins
ffff8000810e8870 d nand_ce1_pins
ffff8000810e8878 d nand_rb0_pins
ffff8000810e8880 d nand_ren_wr_pins
ffff8000810e8888 d nand_ce0_pins
ffff8000810e8890 d nand_cle_pins
ffff8000810e8898 d nand_ale_pins
ffff8000810e88a0 d nand_wen_clk_pins
ffff8000810e88a8 d emmc_nand_ds_pins
ffff8000810e88b0 d emmc_cmd_pins
ffff8000810e88b8 d emmc_clk_pins
ffff8000810e88c0 d emmc_nand_d7_pins
ffff8000810e88c8 d emmc_nand_d6_pins
ffff8000810e88d0 d emmc_nand_d5_pins
ffff8000810e88d8 d emmc_nand_d4_pins
ffff8000810e88e0 d emmc_nand_d3_pins
ffff8000810e88e8 d emmc_nand_d2_pins
ffff8000810e88f0 d emmc_nand_d1_pins
ffff8000810e88f8 d emmc_nand_d0_pins
ffff8000810e8900 d meson_g12a_aobus_pins
ffff8000810e8a68 d meson_g12a_periphs_pins
ffff8000810e9260 d meson_a1_pinctrl_dt_match
ffff8000810e93f0 d meson_a1_periphs_pinctrl_data
ffff8000810e9448 d meson_a1_periphs_pmx_banks_data
ffff8000810e9458 d meson_a1_periphs_pmx_banks
ffff8000810e94d0 d meson_a1_periphs_banks
ffff8000810e9638 d meson_a1_periphs_functions
ffff8000810e99f8 d mute_groups
ffff8000810e9a08 d tst_out_groups
ffff8000810e9a68 d tdm_vad_groups
ffff8000810e9a88 d mclk_vad_groups
ffff8000810e9a90 d tdm_b_groups
ffff8000810e9af8 d mclk_0_groups
ffff8000810e9b00 d clk12_24_groups
ffff8000810e9b08 d cec_b_groups
ffff8000810e9b10 d cec_a_groups
ffff8000810e9b18 d clk25_groups
ffff8000810e9b20 d sw_groups
ffff8000810e9b30 d spdif_in_groups
ffff8000810e9b40 d remote_out_groups
ffff8000810e9b48 d clk_32k_in_groups
ffff8000810e9b50 d jtag_a_groups
ffff8000810e9b70 d remote_input_groups
ffff8000810e9b80 d gen_clk_groups
ffff8000810e9ba0 d pdm_groups
ffff8000810e9be0 d spi_a_groups
ffff8000810e9c40 d i2c3_groups
ffff8000810e9c60 d i2c2_groups
ffff8000810e9ca0 d i2c1_groups
ffff8000810e9cc0 d i2c0_groups
ffff8000810e9ce0 d uart_c_groups
ffff8000810e9d10 d uart_b_groups
ffff8000810e9d30 d uart_a_groups
ffff8000810e9d50 d tdm_a_groups
ffff8000810e9d90 d sdcard_groups
ffff8000810e9df0 d spif_groups
ffff8000810e9e20 d pwm_c_hiz_groups
ffff8000810e9e28 d pwm_b_hiz_groups
ffff8000810e9e30 d pwm_a_hiz_groups
ffff8000810e9e48 d pwm_f_groups
ffff8000810e9e68 d pwm_e_groups
ffff8000810e9e98 d pwm_d_groups
ffff8000810e9eb8 d pwm_c_groups
ffff8000810e9ed8 d pwm_b_groups
ffff8000810e9ef0 d pwm_a_groups
ffff8000810e9f18 d psram_groups
ffff8000810e9f80 d gpio_periphs_groups
ffff8000810ea170 d meson_a1_periphs_groups
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ffff8000810ecd58 d i2c_slave_sda_a_pins
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ffff8000810ecd68 d i2c3_sda_x_pins
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ffff8000810ecd80 d i2c3_sck_f_pins
ffff8000810ecd88 d i2c2_sda_a9_pins
ffff8000810ecd90 d i2c2_sck_a8_pins
ffff8000810ecd98 d i2c2_sda_a5_pins
ffff8000810ecda0 d i2c2_sck_a4_pins
ffff8000810ecda8 d i2c2_sda_x16_pins
ffff8000810ecdb0 d i2c2_sck_x15_pins
ffff8000810ecdb8 d i2c2_sda_x1_pins
ffff8000810ecdc0 d i2c2_sck_x0_pins
ffff8000810ecdc8 d i2c1_sck_a_pins
ffff8000810ecdd0 d i2c1_sda_a_pins
ffff8000810ecdd8 d i2c1_sck_x_pins
ffff8000810ecde0 d i2c1_sda_x_pins
ffff8000810ecde8 d i2c0_sda_f12_pins
ffff8000810ecdf0 d i2c0_sck_f11_pins
ffff8000810ecdf8 d i2c0_sda_f10_pins
ffff8000810ece00 d i2c0_sck_f9_pins
ffff8000810ece08 d spif_cs_pins
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ffff8000810ece18 d spif_hold_n_pins
ffff8000810ece20 d spif_wp_n_pins
ffff8000810ece28 d spif_mi_pins
ffff8000810ece30 d spif_mo_pins
ffff8000810ece38 d sdcard_cmd_x_pins
ffff8000810ece40 d sdcard_clk_x_pins
ffff8000810ece48 d sdcard_d3_x_pins
ffff8000810ece50 d sdcard_d2_x_pins
ffff8000810ece58 d sdcard_d1_x_pins
ffff8000810ece60 d sdcard_d0_x_pins
ffff8000810ece68 d sdcard_cmd_b_pins
ffff8000810ece70 d sdcard_clk_b_pins
ffff8000810ece78 d sdcard_d3_b_pins
ffff8000810ece80 d sdcard_d2_b_pins
ffff8000810ece88 d sdcard_d1_b_pins
ffff8000810ece90 d sdcard_d0_b_pins
ffff8000810ece98 d psram_dqs_dm_pins
ffff8000810ecea0 d psram_adq7_pins
ffff8000810ecea8 d psram_adq6_pins
ffff8000810eceb0 d psram_adq5_pins
ffff8000810eceb8 d psram_adq4_pins
ffff8000810ecec0 d psram_adq3_pins
ffff8000810ecec8 d psram_adq2_pins
ffff8000810eced0 d psram_adq1_pins
ffff8000810eced8 d psram_adq0_pins
ffff8000810ecee0 d psram_rst_n_pins
ffff8000810ecee8 d psram_ce_n_pins
ffff8000810ecef0 d psram_clkp_pins
ffff8000810ecef8 d psram_clkn_pins
ffff8000810ecf00 d meson_a1_periphs_pins
ffff8000810ed4d0 d meson_s4_pinctrl_dt_match
ffff8000810ed660 d meson_s4_periphs_pinctrl_data
ffff8000810ed6b8 d meson_s4_periphs_pmx_banks_data
ffff8000810ed6c8 d meson_s4_periphs_pmx_banks
ffff8000810ed788 d meson_s4_periphs_banks
ffff8000810ed9c8 d meson_s4_periphs_functions
ffff8000810edf20 d s2_demod_groups
ffff8000810edf60 d diseqc_out_groups
ffff8000810edf68 d tsin_b1_groups
ffff8000810edf88 d tsin_b_groups
ffff8000810edfc8 d tsin_a_groups
ffff8000810edfe8 d dtv_groups
ffff8000810ee010 d i2c_slave_groups
ffff8000810ee020 d sdio_groups
ffff8000810ee050 d gen_clk_groups
ffff8000810ee068 d spi_a_groups
ffff8000810ee0d8 d eth_groups
ffff8000810ee0e8 d spdif_in_groups
ffff8000810ee0f0 d spdif_out_groups
ffff8000810ee100 d ao_cec_b_groups
ffff8000810ee108 d ao_cec_a_groups
ffff8000810ee110 d hdmitx_groups
ffff8000810ee128 d mic_mute_groups
ffff8000810ee138 d pwm_j_groups
ffff8000810ee140 d pwm_i_groups
ffff8000810ee150 d pwm_h_groups
ffff8000810ee158 d pwm_g_groups
ffff8000810ee168 d pwm_f_groups
ffff8000810ee178 d pwm_e_groups
ffff8000810ee188 d pwm_d_groups
ffff8000810ee198 d pwm_c_groups
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ffff8000810ee1c0 d pwm_g_hiz_groups
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ffff8000810ee1d0 d pwm_b_hiz_groups
ffff8000810ee1d8 d pwm_a_hiz_groups
ffff8000810ee1e0 d clk_32k_in_groups
ffff8000810ee1e8 d clk12_24_groups
ffff8000810ee1f0 d remote_in_groups
ffff8000810ee1f8 d remote_out_groups
ffff8000810ee200 d mclk_2_groups
ffff8000810ee208 d mclk_1_groups
ffff8000810ee228 d tdm_groups
ffff8000810ee2f8 d iso7816_groups
ffff8000810ee318 d pdm_groups
ffff8000810ee390 d jtag_2_groups
ffff8000810ee3b0 d jtag_1_groups
ffff8000810ee3d0 d sdcard_groups
ffff8000810ee438 d spif_groups
ffff8000810ee468 d nand_groups
ffff8000810ee4d0 d emmc_groups
ffff8000810ee530 d uart_e_groups
ffff8000810ee560 d uart_d_groups
ffff8000810ee5a0 d uart_c_groups
ffff8000810ee5b0 d uart_b_groups
ffff8000810ee5f0 d uart_a_groups
ffff8000810ee610 d i2c4_groups
ffff8000810ee640 d i2c3_groups
ffff8000810ee660 d i2c2_groups
ffff8000810ee690 d i2c1_groups
ffff8000810ee6d0 d i2c0_groups
ffff8000810ee6e0 d gpio_periphs_groups
ffff8000810ee970 d meson_s4_periphs_groups
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ffff8000810f1e80 d gen_clk_z9_pins
ffff8000810f1e88 d s2_demod_gpio0_pins
ffff8000810f1e90 d s2_demod_gpio1_pins
ffff8000810f1e98 d diseqc_out_pins
ffff8000810f1ea0 d s2_demod_gpio2_pins
ffff8000810f1ea8 d s2_demod_gpio3_pins
ffff8000810f1eb0 d s2_demod_gpio4_pins
ffff8000810f1eb8 d s2_demod_gpio5_pins
ffff8000810f1ec0 d s2_demod_gpio6_pins
ffff8000810f1ec8 d s2_demod_gpio7_pins
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ffff8000810f1ef0 d pwm_e_z_pins
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ffff8000810f1f08 d uart_d_rts_z_pins
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ffff8000810f1f20 d uart_d_tx_z_pins
ffff8000810f1f28 d i2c4_sda_z_pins
ffff8000810f1f30 d i2c4_scl_z_pins
ffff8000810f1f38 d spi_a_ss2_z_pins
ffff8000810f1f40 d spi_a_ss1_z_pins
ffff8000810f1f48 d spi_a_ss0_z_pins
ffff8000810f1f50 d spi_a_clk_z_pins
ffff8000810f1f58 d spi_a_mosi_z_pins
ffff8000810f1f60 d spi_a_miso_z_pins
ffff8000810f1f68 d pdm_dclk_z_pins
ffff8000810f1f70 d pdm_din0_z_pins
ffff8000810f1f78 d pdm_din1_z_pins
ffff8000810f1f80 d uart_e_rx_z9_pins
ffff8000810f1f88 d uart_e_tx_z8_pins
ffff8000810f1f90 d sdcard_cmd_z_pins
ffff8000810f1f98 d sdcard_clk_z_pins
ffff8000810f1fa0 d sdcard_d3_z_pins
ffff8000810f1fa8 d sdcard_d2_z_pins
ffff8000810f1fb0 d sdcard_d1_z_pins
ffff8000810f1fb8 d sdcard_d0_z_pins
ffff8000810f1fc0 d dtv_b_rf_agc_pins
ffff8000810f1fc8 d dtv_a_rf_agc_pins
ffff8000810f1fd0 d i2c3_scl_z_pins
ffff8000810f1fd8 d i2c3_sda_z_pins
ffff8000810f1fe0 d dtv_b_if_agc_pins
ffff8000810f1fe8 d dtv_a_if_agc_z6_pins
ffff8000810f1ff0 d tsin_a_din0_pins
ffff8000810f1ff8 d tsin_a_valid_pins
ffff8000810f2000 d tsin_a_sop_pins
ffff8000810f2008 d tsin_a_clk_pins
ffff8000810f2010 d uart_e_rx_z12_pins
ffff8000810f2018 d uart_e_tx_z11_pins
ffff8000810f2020 d dtv_a_if_agc_z10_pins
ffff8000810f2028 d spdif_out_z_pins
ffff8000810f2030 d mclk_2_pins
ffff8000810f2038 d tdm_d7_pins
ffff8000810f2040 d tdm_d6_pins
ffff8000810f2048 d tdm_d5_z_pins
ffff8000810f2050 d tdm_d4_z_pins
ffff8000810f2058 d tdm_sclk2_pins
ffff8000810f2060 d tdm_fs2_pins
ffff8000810f2068 d i2c3_scl_x_pins
ffff8000810f2070 d i2c3_sda_x_pins
ffff8000810f2078 d i2c_slave_sda_pins
ffff8000810f2080 d i2c_slave_scl_pins
ffff8000810f2088 d pwm_c_x_pins
ffff8000810f2090 d spi_a_clk_x_pins
ffff8000810f2098 d spi_a_ss0_x_pins
ffff8000810f20a0 d spi_a_miso_x_pins
ffff8000810f20a8 d spi_a_mosi_x_pins
ffff8000810f20b0 d pdm_dclk_x_pins
ffff8000810f20b8 d pdm_din1_x_pins
ffff8000810f20c0 d pdm_din0_x_pins
ffff8000810f20c8 d pwm_b_x_pins
ffff8000810f20d0 d i2c1_scl_x_pins
ffff8000810f20d8 d i2c1_sda_x_pins
ffff8000810f20e0 d pwm_e_x_pins
ffff8000810f20e8 d uart_a_rts_pins
ffff8000810f20f0 d uart_a_cts_pins
ffff8000810f20f8 d uart_a_rx_pins
ffff8000810f2100 d uart_a_tx_pins
ffff8000810f2108 d tdm_sclk0_pins
ffff8000810f2110 d tdm_fs0_pins
ffff8000810f2118 d tdm_d0_pins
ffff8000810f2120 d tdm_d1_pins
ffff8000810f2128 d pwm_f_x_pins
ffff8000810f2130 d pwm_a_x_pins
ffff8000810f2138 d sdio_cmd_pins
ffff8000810f2140 d sdio_clk_pins
ffff8000810f2148 d sdio_d3_pins
ffff8000810f2150 d sdio_d2_pins
ffff8000810f2158 d sdio_d1_pins
ffff8000810f2160 d sdio_d0_pins
ffff8000810f2168 d tsin_b1_d0_pins
ffff8000810f2170 d tsin_b1_valid_pins
ffff8000810f2178 d tsin_b1_sop_pins
ffff8000810f2180 d tsin_b1_clk_pins
ffff8000810f2188 d gen_clk_h_pins
ffff8000810f2190 d spi_a_ss0_h_pins
ffff8000810f2198 d spi_a_clk_h_pins
ffff8000810f21a0 d spi_a_mosi_h_pins
ffff8000810f21a8 d spi_a_miso_h_pins
ffff8000810f21b0 d tdm_d4_h_pins
ffff8000810f21b8 d tdm_d3_h_pins
ffff8000810f21c0 d tdm_d2_h_pins
ffff8000810f21c8 d tdm_fs1_h_pins
ffff8000810f21d0 d tdm_sclk1_h_pins
ffff8000810f21d8 d mclk_1_h_pins
ffff8000810f21e0 d pdm_din1_h_pins
ffff8000810f21e8 d pdm_din0_h_pins
ffff8000810f21f0 d pdm_dclk_h_pins
ffff8000810f21f8 d pwm_i_h_pins
ffff8000810f2200 d pwm_d_h_pins
ffff8000810f2208 d uart_e_rx_h_pins
ffff8000810f2210 d uart_e_tx_h_pins
ffff8000810f2218 d iso7816_data_h_pins
ffff8000810f2220 d iso7816_clk_h_pins
ffff8000810f2228 d uart_d_rts_h_pins
ffff8000810f2230 d uart_d_cts_h_pins
ffff8000810f2238 d uart_d_rx_h_pins
ffff8000810f2240 d uart_d_tx_h_pins
ffff8000810f2248 d ao_cec_b_pins
ffff8000810f2250 d i2c2_scl_h1_pins
ffff8000810f2258 d i2c2_sda_h0_pins
ffff8000810f2260 d eth_act_led_pins
ffff8000810f2268 d eth_link_led_pins
ffff8000810f2270 d i2c2_scl_h9_pins
ffff8000810f2278 d i2c2_sda_h8_pins
ffff8000810f2280 d i2c1_scl_h_pins
ffff8000810f2288 d i2c1_sda_h_pins
ffff8000810f2290 d spdif_in_pins
ffff8000810f2298 d spdif_out_h_pins
ffff8000810f22a0 d ao_cec_a_pins
ffff8000810f22a8 d hdmitx_hpd_in_pins
ffff8000810f22b0 d hdmitx_sck_pins
ffff8000810f22b8 d hdmitx_sda_pins
ffff8000810f22c0 d tsin_b_d0_c_pins
ffff8000810f22c8 d tsin_b_valid_c_pins
ffff8000810f22d0 d tsin_b_sop_c_pins
ffff8000810f22d8 d tsin_b_clk_c_pins
ffff8000810f22e0 d gen_clk_d_pins
ffff8000810f22e8 d i2c2_scl_d_pins
ffff8000810f22f0 d i2c2_sda_d_pins
ffff8000810f22f8 d i2c1_scl_d_pins
ffff8000810f2300 d i2c1_sda_d_pins
ffff8000810f2308 d mic_mute_key_pins
ffff8000810f2310 d mic_mute_en_pins
ffff8000810f2318 d pdm_din1_d_pins
ffff8000810f2320 d pdm_din0_d_pins
ffff8000810f2328 d pdm_dclk_d_pins
ffff8000810f2330 d pwm_c_hiz_pins
ffff8000810f2338 d pwm_a_hiz_pins
ffff8000810f2340 d pwm_b_hiz_pins
ffff8000810f2348 d clk_32k_in_pins
ffff8000810f2350 d pwm_i_d_pins
ffff8000810f2358 d pwm_d_d_pins
ffff8000810f2360 d pwm_c_d_pins
ffff8000810f2368 d pwm_a_d_pins
ffff8000810f2370 d pwm_b_d_pins
ffff8000810f2378 d uart_c_rx_pins
ffff8000810f2380 d uart_c_tx_pins
ffff8000810f2388 d pwm_g_d_pins
ffff8000810f2390 d tdm_d2_d_pins
ffff8000810f2398 d tdm_d3_d_pins
ffff8000810f23a0 d tdm_d4_d_pins
ffff8000810f23a8 d tdm_fs1_d_pins
ffff8000810f23b0 d tdm_sclk1_d_pins
ffff8000810f23b8 d mclk_1_d_pins
ffff8000810f23c0 d i2c4_scl_d_pins
ffff8000810f23c8 d i2c4_sda_d_pins
ffff8000810f23d0 d pwm_g_hiz_pins
ffff8000810f23d8 d clk12_24_pins
ffff8000810f23e0 d jtag_1_tdo_pins
ffff8000810f23e8 d jtag_1_tdi_pins
ffff8000810f23f0 d jtag_1_tms_pins
ffff8000810f23f8 d jtag_1_clk_pins
ffff8000810f2400 d remote_in_pins
ffff8000810f2408 d remote_out_pins
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ffff8000810f7620 d uart_f_rx_a_pins
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ffff8000810f7630 d lcd_clk_a_pins
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ffff8000810f7640 d jtag_a_tdi_pins
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ffff8000810f7670 d pwm_c_hiz_pins
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ffff8000810f7680 d i2c1_sda_a_pins
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ffff8000810f76c8 d tdm_d0_d_pins
ffff8000810f76d0 d tdm_d1_d_pins
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ffff8000810f76f8 d i2c3_sda_d_pins
ffff8000810f7700 d pwm_j_d_pins
ffff8000810f7708 d pwm_i_d_pins
ffff8000810f7710 d ir_out_pins
ffff8000810f7718 d ir_in_d0_pins
ffff8000810f7720 d ir_in_d6_pins
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ffff8000810f7778 d spi_b_miso_d_pins
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ffff8000810f7828 d pwm_h_x9_pins
ffff8000810f7830 d pwm_g_x8_pins
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ffff8000810f7850 d pwm_k_x4_pins
ffff8000810f7858 d pwm_j_x3_pins
ffff8000810f7860 d pwm_i_x2_pins
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ffff8000810f78b0 d lcd_d14_pins
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ffff8000810f78d0 d lcd_d10_pins
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ffff8000810f7900 d pdm_din0_x6_pins
ffff8000810f7908 d pdm_dclk_x5_pins
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ffff8000810f7968 d spi_b_miso_x_pins
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ffff8000810f7a28 d i2c3_sda_c_pins
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ffff8000810f7a50 d pwm_m_c_pins
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ffff8000810f7a68 d pwm_j_c_pins
ffff8000810f7a70 d pwm_i_c_pins
ffff8000810f7a78 d pwm_h_c_pins
ffff8000810f7a80 d pwm_g_c_pins
ffff8000810f7a88 d spi_a_ss1_c_pins
ffff8000810f7a90 d spi_a_ss0_c_pins
ffff8000810f7a98 d spi_a_clk_c_pins
ffff8000810f7aa0 d spi_a_miso_c_pins
ffff8000810f7aa8 d spi_a_mosi_c_pins
ffff8000810f7ab0 d pdm_din0_c_pins
ffff8000810f7ab8 d pdm_dclk_c_pins
ffff8000810f7ac0 d tdm_fs1_pins
ffff8000810f7ac8 d tdm_sclk1_pins
ffff8000810f7ad0 d mclk_1_pins
ffff8000810f7ad8 d tdm_d2_pins
ffff8000810f7ae0 d tdm_d3_pins
ffff8000810f7ae8 d gen_clk_c_pins
ffff8000810f7af0 d jtag_b_tms_pins
ffff8000810f7af8 d jtag_b_clk_pins
ffff8000810f7b00 d uart_b_tx_c_pins
ffff8000810f7b08 d uart_b_rx_c_pins
ffff8000810f7b10 d jtag_b_tdi_pins
ffff8000810f7b18 d jtag_b_tdo_pins
ffff8000810f7b20 d sdcard_cd_pins
ffff8000810f7b28 d sdcard_cmd_pins
ffff8000810f7b30 d sdcard_clk_pins
ffff8000810f7b38 d sdcard_d3_pins
ffff8000810f7b40 d sdcard_d2_pins
ffff8000810f7b48 d sdcard_d1_pins
ffff8000810f7b50 d sdcard_d0_pins
ffff8000810f7b58 d pdm_din0_b_pins
ffff8000810f7b60 d pdm_dclk_b_pins
ffff8000810f7b68 d uart_d_rx_b_pins
ffff8000810f7b70 d uart_d_tx_b_pins
ffff8000810f7b78 d uart_a_rts_b_pins
ffff8000810f7b80 d uart_a_cts_b_pins
ffff8000810f7b88 d uart_a_rx_b_pins
ffff8000810f7b90 d uart_a_tx_b_pins
ffff8000810f7b98 d i2c1_scl_b_pins
ffff8000810f7ba0 d i2c1_sda_b_pins
ffff8000810f7ba8 d spi_a_ss2_b_pins
ffff8000810f7bb0 d spi_a_ss1_b_pins
ffff8000810f7bb8 d spi_a_ss0_b_pins
ffff8000810f7bc0 d spi_a_clk_b_pins
ffff8000810f7bc8 d spi_a_miso_b_pins
ffff8000810f7bd0 d spi_a_mosi_b_pins
ffff8000810f7bd8 d lcd_d7_pins
ffff8000810f7be0 d lcd_d6_pins
ffff8000810f7be8 d lcd_d5_pins
ffff8000810f7bf0 d lcd_d4_pins
ffff8000810f7bf8 d lcd_d3_pins
ffff8000810f7c00 d lcd_d2_pins
ffff8000810f7c08 d lcd_d1_pins
ffff8000810f7c10 d lcd_d0_pins
ffff8000810f7c18 d spif_clk_loop_pins
ffff8000810f7c20 d spif_cs_pins
ffff8000810f7c28 d pwm_n_b_pins
ffff8000810f7c30 d pwm_m_b_pins
ffff8000810f7c38 d pwm_l_b_pins
ffff8000810f7c40 d pwm_k_b_pins
ffff8000810f7c48 d pwm_j_b_pins
ffff8000810f7c50 d spif_wp_pins
ffff8000810f7c58 d spif_clk_pins
ffff8000810f7c60 d spif_mi_pins
ffff8000810f7c68 d spif_mo_pins
ffff8000810f7c70 d spif_hold_pins
ffff8000810f7c78 d pwm_i_b_pins
ffff8000810f7c80 d pwm_h_b_pins
ffff8000810f7c88 d pwm_g_b_pins
ffff8000810f7c90 d nand_ce0_pins
ffff8000810f7c98 d nand_cle_pins
ffff8000810f7ca0 d nand_ren_wr_pins
ffff8000810f7ca8 d nand_ale_pins
ffff8000810f7cb0 d nand_wen_clk_pins
ffff8000810f7cb8 d emmc_nand_ds_pins
ffff8000810f7cc0 d emmc_cmd_pins
ffff8000810f7cc8 d emmc_rst_pins
ffff8000810f7cd0 d emmc_clk_pins
ffff8000810f7cd8 d emmc_nand_d7_pins
ffff8000810f7ce0 d emmc_nand_d6_pins
ffff8000810f7ce8 d emmc_nand_d5_pins
ffff8000810f7cf0 d emmc_nand_d4_pins
ffff8000810f7cf8 d emmc_nand_d3_pins
ffff8000810f7d00 d emmc_nand_d2_pins
ffff8000810f7d08 d emmc_nand_d1_pins
ffff8000810f7d10 d emmc_nand_d0_pins
ffff8000810f7d18 d clk12_24_e_pins
ffff8000810f7d20 d i2c_slave_sda_pins
ffff8000810f7d28 d i2c_slave_scl_pins
ffff8000810f7d30 d clk_32k_in_pins
ffff8000810f7d38 d i2c0_scl_e_pins
ffff8000810f7d40 d i2c0_sda_e_pins
ffff8000810f7d48 d gen_clk_e_pins
ffff8000810f7d50 d i2c2_scl_pins
ffff8000810f7d58 d i2c2_sda_pins
ffff8000810f7d60 d pwm_b_pins
ffff8000810f7d68 d pwm_a_pins
ffff8000810f7d70 d c3_periphs_pins
ffff8000810f8298 d t7_pinctrl_dt_match
ffff8000810f8428 d t7_periphs_pinctrl_data
ffff8000810f8480 d t7_periphs_pmx_banks_data
ffff8000810f8490 d t7_periphs_pmx_banks
ffff8000810f85b0 d t7_periphs_banks
ffff8000810f8910 d t7_periphs_functions
ffff8000810f9060 d mic_mute_groups
ffff8000810f9070 d edp_b_groups
ffff8000810f9078 d edp_a_groups
ffff8000810f9080 d vx1_b_groups
ffff8000810f9090 d vx1_a_groups
ffff8000810f90a0 d sync_3d_groups
ffff8000810f90a8 d vsync_groups
ffff8000810f90b0 d hsync_groups
ffff8000810f90b8 d pcieck_groups
ffff8000810f90c8 d pdm_groups
ffff8000810f90f8 d mclk_groups
ffff8000810f9108 d tsin_d_groups
ffff8000810f9148 d tsin_c_groups
ffff8000810f9188 d tsin_b_groups
ffff8000810f91e8 d tsin_a_groups
ffff8000810f9208 d iso7816_groups
ffff8000810f9228 d eth_groups
ffff8000810f92a8 d clk25m_groups
ffff8000810f92b0 d spdif_in_groups
ffff8000810f92c0 d spdif_out_groups
ffff8000810f92d0 d rtc_clk_groups
ffff8000810f92e0 d wd_rsto_groups
ffff8000810f92e8 d remote_in_groups
ffff8000810f92f0 d remote_out_groups
ffff8000810f9300 d hdmitx_groups
ffff8000810f9328 d cec_b_groups
ffff8000810f9330 d cec_a_groups
ffff8000810f9338 d hdmirx_c_groups
ffff8000810f9358 d hdmirx_b_groups
ffff8000810f9378 d hdmirx_a_groups
ffff8000810f9398 d clk12_24_groups
ffff8000810f93a8 d i2c5_groups
ffff8000810f93b8 d i2c4_groups
ffff8000810f93d8 d i2c3_groups
ffff8000810f93f8 d i2c2_groups
ffff8000810f9428 d i2c1_groups
ffff8000810f9438 d i2c0_groups
ffff8000810f9458 d i2c1_ao_groups
ffff8000810f9468 d i2c0_ao_groups
ffff8000810f9488 d i2c0_slave_ao_groups
ffff8000810f9498 d tdm_groups
ffff8000810f9558 d pwm_vs_groups
ffff8000810f9568 d pwm_ao_g_groups
ffff8000810f9580 d pwm_ao_h_groups
ffff8000810f9590 d pwm_ao_f_groups
ffff8000810f9598 d pwm_ao_e_groups
ffff8000810f95a0 d pwm_ao_d_groups
ffff8000810f95a8 d pwm_ao_c_groups
ffff8000810f95b8 d pwm_ao_b_groups
ffff8000810f95c0 d pwm_ao_a_groups
ffff8000810f95c8 d pwm_ao_g_hiz_groups
ffff8000810f95d0 d pwm_ao_c_hiz_groups
ffff8000810f95d8 d pwm_f_groups
ffff8000810f95e0 d pwm_e_groups
ffff8000810f95e8 d pwm_d_groups
ffff8000810f95f0 d pwm_c_groups
ffff8000810f95f8 d pwm_b_groups
ffff8000810f9600 d pwm_a_groups
ffff8000810f9608 d spi5_groups
ffff8000810f9628 d spi4_groups
ffff8000810f9648 d spi3_groups
ffff8000810f9668 d spi2_groups
ffff8000810f9698 d spi1_groups
ffff8000810f96e8 d spi0_groups
ffff8000810f9718 d uart_ao_b_groups
ffff8000810f9738 d uart_ao_a_groups
ffff8000810f9788 d uart_f_groups
ffff8000810f97a8 d uart_e_groups
ffff8000810f97c8 d uart_d_groups
ffff8000810f9808 d uart_c_groups
ffff8000810f9828 d jtag_b_groups
ffff8000810f9848 d jtag_a_groups
ffff8000810f9868 d gen_clk_groups
ffff8000810f9878 d sdio_groups
ffff8000810f98a8 d sdcard_groups
ffff8000810f98d8 d nor_groups
ffff8000810f9908 d emmc_groups
ffff8000810f9960 d gpio_periphs_groups
ffff8000810f9e48 d t7_periphs_groups
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ffff8000810fe800 d __compound_literal.22
ffff8000810fe808 d __compound_literal.21
ffff8000810fe810 d __compound_literal.20
ffff8000810fe818 d __compound_literal.19
ffff8000810fe820 d __compound_literal.18
ffff8000810fe828 d __compound_literal.17
ffff8000810fe830 d __compound_literal.16
ffff8000810fe838 d __compound_literal.15
ffff8000810fe840 d __compound_literal.14
ffff8000810fe848 d __compound_literal.13
ffff8000810fe850 d __compound_literal.12
ffff8000810fe858 d __compound_literal.11
ffff8000810fe860 d __compound_literal.10
ffff8000810fe868 d __compound_literal.9
ffff8000810fe870 d __compound_literal.8
ffff8000810fe878 d __compound_literal.7
ffff8000810fe880 d __compound_literal.6
ffff8000810fe888 d __compound_literal.5
ffff8000810fe890 d __compound_literal.4
ffff8000810fe898 d __compound_literal.3
ffff8000810fe8a0 d __compound_literal.2
ffff8000810fe8a8 d __compound_literal.1
ffff8000810fe8b0 d __compound_literal.0
ffff8000810fe8b8 d pcieck_reqn_h_pins
ffff8000810fe8c0 d i2c0_sck_h_pins
ffff8000810fe8c8 d i2c0_sda_h_pins
ffff8000810fe8d0 d uart_f_rts_pins
ffff8000810fe8d8 d uart_f_cts_pins
ffff8000810fe8e0 d uart_f_rx_pins
ffff8000810fe8e8 d uart_f_tx_pins
ffff8000810fe8f0 d pwm_vs_h_pins
ffff8000810fe8f8 d eth_act_led_pins
ffff8000810fe900 d eth_link_led_pins
ffff8000810fe908 d i2c4_sda_h_pins
ffff8000810fe910 d i2c4_sck_h_pins
ffff8000810fe918 d i2c3_sda_h_pins
ffff8000810fe920 d i2c3_sck_h_pins
ffff8000810fe928 d mic_mute_led_pins
ffff8000810fe930 d mic_mute_key_pins
ffff8000810fe938 d edp_b_hpd_pins
ffff8000810fe940 d edp_a_hpd_pins
ffff8000810fe948 d pwm_vs_y_pins
ffff8000810fe950 d vx1_b_lockn_pins
ffff8000810fe958 d vx1_a_lockn_pins
ffff8000810fe960 d vx1_b_htpdn_pins
ffff8000810fe968 d vx1_a_htpdn_pins
ffff8000810fe970 d sync_3d_out_pins
ffff8000810fe978 d pwm_f_pins
ffff8000810fe980 d vsync_pins
ffff8000810fe988 d hsync_pins
ffff8000810fe990 d pwm_e_pins
ffff8000810fe998 d pcieck_reqn_y_pins
ffff8000810fe9a0 d tsin_d_y_valid_pins
ffff8000810fe9a8 d tsin_d_y_clk_pins
ffff8000810fe9b0 d tsin_d_y_din0_pins
ffff8000810fe9b8 d tsin_d_y_sop_pins
ffff8000810fe9c0 d tsin_c_y_valid_pins
ffff8000810fe9c8 d tsin_c_y_clk_pins
ffff8000810fe9d0 d tsin_c_y_din0_pins
ffff8000810fe9d8 d tsin_c_y_sop_pins
ffff8000810fe9e0 d i2c5_sda_pins
ffff8000810fe9e8 d i2c5_sck_pins
ffff8000810fe9f0 d i2c4_sda_y_pins
ffff8000810fe9f8 d i2c4_sck_y_pins
ffff8000810fea00 d uart_d_rx_y_pins
ffff8000810fea08 d uart_d_tx_y_pins
ffff8000810fea10 d uart_d_rts_y_pins
ffff8000810fea18 d uart_d_cts_y_pins
ffff8000810fea20 d uart_e_rts_pins
ffff8000810fea28 d uart_e_cts_pins
ffff8000810fea30 d uart_e_rx_pins
ffff8000810fea38 d uart_e_tx_pins
ffff8000810fea40 d spi2_ss2_pins
ffff8000810fea48 d spi2_ss1_pins
ffff8000810fea50 d spi2_ss0_pins
ffff8000810fea58 d spi2_sclk_pins
ffff8000810fea60 d spi2_miso_pins
ffff8000810fea68 d spi2_mosi_pins
ffff8000810fea70 d i2c2_sck_m_pins
ffff8000810fea78 d i2c2_sda_m_pins
ffff8000810fea80 d uart_d_rts_m_pins
ffff8000810fea88 d uart_d_cts_m_pins
ffff8000810fea90 d uart_d_rx_m_pins
ffff8000810fea98 d uart_d_tx_m_pins
ffff8000810feaa0 d pdm_din1_m5_pins
ffff8000810feaa8 d pdm_din0_pins
ffff8000810feab0 d pdm_dclk_pins
ffff8000810feab8 d pdm_din3_pins
ffff8000810feac0 d pdm_din2_pins
ffff8000810feac8 d pdm_din1_m0_pins
ffff8000810fead0 d spi1_ss2_m_pins
ffff8000810fead8 d spi1_ss1_m_pins
ffff8000810feae0 d spi1_ss0_m_pins
ffff8000810feae8 d spi1_sclk_m_pins
ffff8000810feaf0 d spi1_miso_m_pins
ffff8000810feaf8 d spi1_mosi_m_pins
ffff8000810feb00 d i2c3_sck_m_pins
ffff8000810feb08 d i2c3_sda_m_pins
ffff8000810feb10 d tdm_fs3_pins
ffff8000810feb18 d tdm_sclk3_pins
ffff8000810feb20 d tdm_d15_pins
ffff8000810feb28 d tdm_d14_pins
ffff8000810feb30 d tdm_d13_pins
ffff8000810feb38 d tdm_d12_pins
ffff8000810feb40 d spi3_ss0_pins
ffff8000810feb48 d spi3_sclk_pins
ffff8000810feb50 d spi3_miso_pins
ffff8000810feb58 d spi3_mosi_pins
ffff8000810feb60 d i2c2_sda_t_pins
ffff8000810feb68 d i2c2_sck_t_pins
ffff8000810feb70 d i2c0_sda_t_pins
ffff8000810feb78 d i2c0_sck_t_pins
ffff8000810feb80 d tsin_a_valid_t_pins
ffff8000810feb88 d tsin_a_clk_t_pins
ffff8000810feb90 d tsin_a_din0_t_pins
ffff8000810feb98 d tsin_a_sop_t_pins
ffff8000810feba0 d iso7816_data_t_pins
ffff8000810feba8 d iso7816_clk_t_pins
ffff8000810febb0 d spdif_out_t_pins
ffff8000810febb8 d spdif_in_t_pins
ffff8000810febc0 d spi0_ss2_pins
ffff8000810febc8 d spi0_ss1_pins
ffff8000810febd0 d spi0_ss0_pins
ffff8000810febd8 d spi0_sclk_pins
ffff8000810febe0 d spi0_miso_pins
ffff8000810febe8 d spi0_mosi_pins
ffff8000810febf0 d i2c1_sda_pins
ffff8000810febf8 d i2c1_sck_pins
ffff8000810fec00 d tdm_fs2_pins
ffff8000810fec08 d tdm_sclk2_pins
ffff8000810fec10 d mclk2_pins
ffff8000810fec18 d tdm_d11_pins
ffff8000810fec20 d tdm_d10_pins
ffff8000810fec28 d tdm_d9_pins
ffff8000810fec30 d tdm_d8_pins
ffff8000810fec38 d tdm_d7_pins
ffff8000810fec40 d tdm_d6_pins
ffff8000810fec48 d tdm_d5_pins
ffff8000810fec50 d tdm_d4_pins
ffff8000810fec58 d tdm_d3_pins
ffff8000810fec60 d tdm_d2_pins
ffff8000810fec68 d tdm_fs1_pins
ffff8000810fec70 d tdm_sclk1_pins
ffff8000810fec78 d mclk1_pins
ffff8000810fec80 d spi5_ss0_pins
ffff8000810fec88 d spi5_sclk_pins
ffff8000810fec90 d spi5_miso_pins
ffff8000810fec98 d spi5_mosi_pins
ffff8000810feca0 d spi4_ss0_pins
ffff8000810feca8 d spi4_sclk_pins
ffff8000810fecb0 d spi4_miso_pins
ffff8000810fecb8 d spi4_mosi_pins
ffff8000810fecc0 d tsin_d_z_clk_pins
ffff8000810fecc8 d tsin_d_z_din0_pins
ffff8000810fecd0 d tsin_d_z_sop_pins
ffff8000810fecd8 d tsin_d_z_valid_pins
ffff8000810fece0 d tsin_c_z_clk_pins
ffff8000810fece8 d tsin_c_z_din0_pins
ffff8000810fecf0 d tsin_c_z_sop_pins
ffff8000810fecf8 d tsin_c_z_valid_pins
ffff8000810fed00 d tsin_b_din7_pins
ffff8000810fed08 d tsin_b_din6_pins
ffff8000810fed10 d tsin_b_din5_pins
ffff8000810fed18 d tsin_b_din4_pins
ffff8000810fed20 d tsin_b_din3_pins
ffff8000810fed28 d tsin_b_din2_pins
ffff8000810fed30 d tsin_b_din1_pins
ffff8000810fed38 d tsin_b_fail_pins
ffff8000810fed40 d tsin_b_clk_pins
ffff8000810fed48 d tsin_b_din0_pins
ffff8000810fed50 d tsin_b_sop_pins
ffff8000810fed58 d tsin_b_valid_pins
ffff8000810fed60 d iso7816_data_z_pins
ffff8000810fed68 d iso7816_clk_z_pins
ffff8000810fed70 d eth_txd3_rgmii_pins
ffff8000810fed78 d eth_txd2_rgmii_pins
ffff8000810fed80 d eth_txd1_pins
ffff8000810fed88 d eth_txd0_pins
ffff8000810fed90 d eth_txen_pins
ffff8000810fed98 d eth_rgmii_tx_clk_pins
ffff8000810feda0 d eth_rxd3_rgmii_pins
ffff8000810feda8 d eth_rxd2_rgmii_pins
ffff8000810fedb0 d eth_rxd1_pins
ffff8000810fedb8 d eth_rxd0_pins
ffff8000810fedc0 d eth_rx_dv_pins
ffff8000810fedc8 d eth_rgmii_rx_clk_pins
ffff8000810fedd0 d eth_mdc_pins
ffff8000810fedd8 d eth_mdio_pins
ffff8000810fede0 d clk12_24_e_pins
ffff8000810fede8 d rtc_clk_out_pins
ffff8000810fedf0 d i2c1_ao_sda_pins
ffff8000810fedf8 d i2c1_ao_sck_pins
ffff8000810fee00 d clk25m_pins
ffff8000810fee08 d i2c0_ao_sda_e_pins
ffff8000810fee10 d i2c0_ao_sck_e_pins
ffff8000810fee18 d pwm_ao_g_e_pins
ffff8000810fee20 d pwm_ao_f_pins
ffff8000810fee28 d pwm_ao_e_pins
ffff8000810fee30 d pwm_ao_d_pins
ffff8000810fee38 d pwm_ao_c_e_pins
ffff8000810fee40 d pwm_ao_b_pins
ffff8000810fee48 d pwm_ao_a_pins
ffff8000810fee50 d remote_out_d6_pins
ffff8000810fee58 d uart_ao_b_rts_pins
ffff8000810fee60 d pwm_ao_g_hiz_pins
ffff8000810fee68 d pwm_ao_c_hiz_pins
ffff8000810fee70 d uart_ao_b_cts_pins
ffff8000810fee78 d uart_ao_b_rx_pins
ffff8000810fee80 d uart_ao_b_tx_pins
ffff8000810fee88 d pwm_ao_h_d10_pins
ffff8000810fee90 d spdif_in_d_pins
ffff8000810fee98 d spdif_out_d_pins
ffff8000810feea0 d pwm_ao_g_d7_pins
ffff8000810feea8 d pwm_ao_c_d_pins
ffff8000810feeb0 d pwm_ao_h_d5_pins
ffff8000810feeb8 d rtc_clk_in_pins
ffff8000810feec0 d i2c0_slave_ao_sda_pins
ffff8000810feec8 d i2c0_slave_ao_sck_pins
ffff8000810feed0 d wd_rsto_pins
ffff8000810feed8 d pwm_ao_g_d11_pins
ffff8000810feee0 d gen_clk_out_d_pins
ffff8000810feee8 d jtag_a_tdo_pins
ffff8000810feef0 d jtag_a_tdi_pins
ffff8000810feef8 d jtag_a_tms_pins
ffff8000810fef00 d jtag_a_clk_pins
ffff8000810fef08 d remote_in_pins
ffff8000810fef10 d remote_out_d4_pins
ffff8000810fef18 d i2c0_ao_sda_d_pins
ffff8000810fef20 d i2c0_ao_sck_d_pins
ffff8000810fef28 d uart_ao_a_rx_d1_pins
ffff8000810fef30 d uart_ao_a_tx_d0_pins
ffff8000810fef38 d hdmitx_sck_w3_pins
ffff8000810fef40 d hdmitx_sda_w2_pins
ffff8000810fef48 d uart_ao_a_rx_w11_pins
ffff8000810fef50 d uart_ao_a_tx_w10_pins
ffff8000810fef58 d uart_ao_a_rx_w7_pins
ffff8000810fef60 d uart_ao_a_tx_w6_pins
ffff8000810fef68 d uart_ao_a_rx_w3_pins
ffff8000810fef70 d uart_ao_a_tx_w2_pins
ffff8000810fef78 d cec_b_pins
ffff8000810fef80 d hdmitx_hpd_in_pins
ffff8000810fef88 d hdmitx_sck_w14_pins
ffff8000810fef90 d hdmitx_sda_w13_pins
ffff8000810fef98 d cec_a_pins
ffff8000810fefa0 d hdmirx_b_sck_pins
ffff8000810fefa8 d hdmirx_b_sda_pins
ffff8000810fefb0 d hdmirx_b_det_pins
ffff8000810fefb8 d hdmirx_b_hpd_pins
ffff8000810fefc0 d hdmirx_c_sck_pins
ffff8000810fefc8 d hdmirx_c_sda_pins
ffff8000810fefd0 d hdmirx_c_det_pins
ffff8000810fefd8 d hdmirx_c_hpd_pins
ffff8000810fefe0 d hdmirx_a_sck_pins
ffff8000810fefe8 d hdmirx_a_sda_pins
ffff8000810feff0 d hdmirx_a_det_pins
ffff8000810feff8 d hdmirx_a_hpd_pins
ffff8000810ff000 d clk12_24_x_pins
ffff8000810ff008 d pwm_d_pins
ffff8000810ff010 d i2c2_sck_x_pins
ffff8000810ff018 d i2c2_sda_x_pins
ffff8000810ff020 d pwm_a_pins
ffff8000810ff028 d uart_c_rts_pins
ffff8000810ff030 d uart_c_cts_pins
ffff8000810ff038 d uart_c_rx_pins
ffff8000810ff040 d uart_c_tx_pins
ffff8000810ff048 d tdm_sclk0_pins
ffff8000810ff050 d tdm_fs0_pins
ffff8000810ff058 d tdm_d1_pins
ffff8000810ff060 d tdm_d0_pins
ffff8000810ff068 d pwm_c_pins
ffff8000810ff070 d pwm_b_pins
ffff8000810ff078 d sdio_cmd_pins
ffff8000810ff080 d sdio_clk_pins
ffff8000810ff088 d sdio_d3_pins
ffff8000810ff090 d sdio_d2_pins
ffff8000810ff098 d sdio_d1_pins
ffff8000810ff0a0 d sdio_d0_pins
ffff8000810ff0a8 d spi1_ss0_c_pins
ffff8000810ff0b0 d spi1_sclk_c_pins
ffff8000810ff0b8 d spi1_miso_c_pins
ffff8000810ff0c0 d spi1_mosi_c_pins
ffff8000810ff0c8 d jtag_b_tms_pins
ffff8000810ff0d0 d jtag_b_clk_pins
ffff8000810ff0d8 d uart_ao_a_tx_c_pins
ffff8000810ff0e0 d uart_ao_a_rx_c_pins
ffff8000810ff0e8 d jtag_b_tdi_pins
ffff8000810ff0f0 d jtag_b_tdo_pins
ffff8000810ff0f8 d gen_clk_out_c_pins
ffff8000810ff100 d sdcard_cmd_pins
ffff8000810ff108 d sdcard_clk_pins
ffff8000810ff110 d sdcard_d3_pins
ffff8000810ff118 d sdcard_d2_pins
ffff8000810ff120 d sdcard_d1_pins
ffff8000810ff128 d sdcard_d0_pins
ffff8000810ff130 d nor_cs_pins
ffff8000810ff138 d nor_wp_pins
ffff8000810ff140 d nor_c_pins
ffff8000810ff148 d nor_q_pins
ffff8000810ff150 d nor_d_pins
ffff8000810ff158 d nor_hold_pins
ffff8000810ff160 d emmc_nand_ds_pins
ffff8000810ff168 d emmc_cmd_pins
ffff8000810ff170 d emmc_clk_pins
ffff8000810ff178 d emmc_nand_d7_pins
ffff8000810ff180 d emmc_nand_d6_pins
ffff8000810ff188 d emmc_nand_d5_pins
ffff8000810ff190 d emmc_nand_d4_pins
ffff8000810ff198 d emmc_nand_d3_pins
ffff8000810ff1a0 d emmc_nand_d2_pins
ffff8000810ff1a8 d emmc_nand_d1_pins
ffff8000810ff1b0 d emmc_nand_d0_pins
ffff8000810ff1b8 d t7_periphs_pins
ffff800081100070 d mvebu_pinctrl_ops
ffff8000811000a0 d mvebu_pinmux_ops
ffff8000811000f8 d mvebu_pinconf_ops
ffff800081100138 d armada_ap806_mpp_controls
ffff800081100170 d armada_ap806_pinctrl_of_match
ffff800081100300 d armada_cp110_mpp_controls
ffff800081100338 d armada_cp110_pinctrl_of_match
ffff800081100720 d armada_37xx_pinctrl_regmap_config
ffff800081100858 d armada_37xx_pctrl_ops
ffff800081100888 d armada_37xx_pmx_ops
ffff8000811008e0 d armada_37xx_pinconf_ops
ffff800081100920 d armada_37xx_irqchip
ffff800081100a30 d __func__.0
ffff800081100a50 d __func__.1
ffff800081100a70 d __func__.2
ffff800081100a98 d armada_37xx_pinctrl_of_match
ffff800081100cf0 d armada_3700_pinctrl_pm_ops
ffff800081100da8 d armada_37xx_pin_sb
ffff800081100dc8 d armada_37xx_pin_nb
ffff800081100de8 d ac5_mpp_controls
ffff800081100e20 d ac5_pinctrl_of_match
ffff800081100fb0 d msm_pinctrl_ops
ffff800081100fe0 d msm_pinmux_ops
ffff800081101038 d msm_pinconf_ops
ffff800081101078 d msm_gpio_irq_chip
ffff800081101188 d pulls_no_keeper.1
ffff8000811011a0 d pulls_keeper.0
ffff8000811011c0 d __func__.2
ffff8000811011d8 D msm_pinctrl_dev_pm_ops
ffff800081101290 d sdm845_pinctrl
ffff8000811012f8 d sdm845_acpi_pinctrl
ffff800081101360 d sdm845_pinctrl_of_match
ffff8000811014f0 d sdm845_pinctrl_acpi_match
ffff800081101530 d sdm845_pdc_map
ffff800081101788 d sdm845_acpi_reserved_gpios
ffff8000811017b0 d sdm845_groups
ffff800081104300 d sdm845_functions
ffff800081105320 d tsif1_sync_groups
ffff800081105328 d m_voc_groups
ffff800081105330 d atest_usb10_groups
ffff800081105338 d wlan2_adc0_groups
ffff800081105340 d dbg_out_groups
ffff800081105348 d edp_lcd_groups
ffff800081105350 d ddr_pxi2_groups
ffff800081105360 d atest_usb11_groups
ffff800081105368 d wlan2_adc1_groups
ffff800081105370 d qup_l6_groups
ffff800081105390 d mdp_vsync_groups
ffff8000811053b8 d atest_usb12_groups
ffff8000811053c0 d wlan1_adc0_groups
ffff8000811053c8 d qup_l5_groups
ffff8000811053e8 d ddr_pxi1_groups
ffff8000811053f8 d atest_usb13_groups
ffff800081105400 d wlan1_adc1_groups
ffff800081105408 d qup_l4_groups
ffff800081105428 d atest_usb1_groups
ffff800081105430 d vsense_trigger_groups
ffff800081105438 d atest_tsens2_groups
ffff800081105440 d ddr_bist_groups
ffff800081105460 d ddr_pxi0_groups
ffff800081105470 d qdss_cti_groups
ffff8000811054b0 d qup9_groups
ffff8000811054d0 d gpio_groups
ffff800081105980 d qup0_groups
ffff8000811059a0 d mss_lte_groups
ffff8000811059b0 d pa_indicator_groups
ffff8000811059b8 d qlink_enable_groups
ffff8000811059c0 d qlink_request_groups
ffff8000811059c8 d adsp_ext_groups
ffff8000811059d0 d atest_char_groups
ffff8000811059f8 d nav_pps_groups
ffff800081105a48 d edp_hot_groups
ffff800081105a50 d uim_batt_groups
ffff800081105a58 d uim1_present_groups
ffff800081105a60 d uim1_reset_groups
ffff800081105a68 d uim1_clk_groups
ffff800081105a70 d uim1_data_groups
ffff800081105a78 d uim2_present_groups
ffff800081105a80 d uim2_reset_groups
ffff800081105a88 d uim2_clk_groups
ffff800081105a90 d qup13_groups
ffff800081105ab0 d uim2_data_groups
ffff800081105ab8 d prng_rosc_groups
ffff800081105ac0 d pci_e1_groups
ffff800081105ad0 d ldo_update_groups
ffff800081105ad8 d ldo_en_groups
ffff800081105ae0 d tsif2_sync_groups
ffff800081105ae8 d qspi_clk_groups
ffff800081105af0 d tsif2_data_groups
ffff800081105af8 d tsif2_en_groups
ffff800081105b00 d qup7_groups
ffff800081105b20 d sdc4_clk_groups
ffff800081105b28 d tsif2_clk_groups
ffff800081105b30 d tgu_ch2_groups
ffff800081105b38 d vfr_1_groups
ffff800081105b40 d sdc4_data_groups
ffff800081105b60 d tsif2_error_groups
ffff800081105b68 d tgu_ch1_groups
ffff800081105b70 d qspi_data_groups
ffff800081105b90 d sdc4_cmd_groups
ffff800081105b98 d tsif1_data_groups
ffff800081105ba0 d tgu_ch0_groups
ffff800081105ba8 d mdp_vsync3_groups
ffff800081105bb0 d mdp_vsync2_groups
ffff800081105bb8 d mdp_vsync1_groups
ffff800081105bc0 d mdp_vsync0_groups
ffff800081105bc8 d tsif1_en_groups
ffff800081105bd0 d tgu_ch3_groups
ffff800081105bd8 d qspi_cs_groups
ffff800081105be8 d qup4_groups
ffff800081105c08 d tsif1_clk_groups
ffff800081105c10 d qup5_groups
ffff800081105c30 d qup15_groups
ffff800081105c50 d sec_mi2s_groups
ffff800081105c78 d atest_usb20_groups
ffff800081105c80 d atest_usb21_groups
ffff800081105c88 d atest_usb22_groups
ffff800081105c90 d atest_usb23_groups
ffff800081105c98 d ter_mi2s_groups
ffff800081105cc0 d atest_usb2_groups
ffff800081105cc8 d btfm_slimbus_groups
ffff800081105cd8 d tsense_pwm2_groups
ffff800081105ce0 d tsense_pwm1_groups
ffff800081105ce8 d audio_ref_groups
ffff800081105cf0 d spkr_i2s_groups
ffff800081105d10 d pri_mi2s_ws_groups
ffff800081105d18 d qup8_groups
ffff800081105d38 d sp_cmu_groups
ffff800081105d40 d pri_mi2s_groups
ffff800081105d60 d cri_trng_groups
ffff800081105d68 d cri_trng1_groups
ffff800081105d70 d cri_trng0_groups
ffff800081105d78 d gcc_gp1_groups
ffff800081105d88 d qua_mi2s_groups
ffff800081105dc0 d qup10_groups
ffff800081105de0 d qup12_groups
ffff800081105e00 d qup6_groups
ffff800081105e20 d qup3_groups
ffff800081105e40 d tsif1_error_groups
ffff800081105e48 d sd_write_groups
ffff800081105e50 d lpass_slimbus_groups
ffff800081105e70 d usb_phy_groups
ffff800081105e78 d agera_pll_groups
ffff800081105e80 d atest_tsens_groups
ffff800081105e88 d pll_bist_groups
ffff800081105e90 d jitter_bist_groups
ffff800081105e98 d pci_e0_groups
ffff800081105ea8 d qup14_groups
ffff800081105ec8 d qup11_groups
ffff800081105ee8 d phase_flag_groups
ffff800081105fe8 d qup2_groups
ffff800081106008 d cci_timer4_groups
ffff800081106010 d cci_async_groups
ffff800081106028 d cci_timer3_groups
ffff800081106030 d cci_timer2_groups
ffff800081106038 d gcc_gp3_groups
ffff800081106048 d cci_timer1_groups
ffff800081106050 d gcc_gp2_groups
ffff800081106060 d cci_timer0_groups
ffff800081106068 d qup1_groups
ffff800081106088 d cci_i2c_groups
ffff8000811060a8 d pll_reset_groups
ffff8000811060b0 d qdss_groups
ffff8000811061d0 d pll_bypassnl_groups
ffff8000811061d8 d cam_mclk_groups
ffff8000811061f8 d ddr_pxi3_groups
ffff800081106208 d sdc2_data_pins
ffff800081106210 d sdc2_cmd_pins
ffff800081106218 d sdc2_clk_pins
ffff800081106220 d ufs_reset_pins
ffff800081106228 d gpio149_pins
ffff800081106230 d gpio148_pins
ffff800081106238 d gpio147_pins
ffff800081106240 d gpio146_pins
ffff800081106248 d gpio145_pins
ffff800081106250 d gpio144_pins
ffff800081106258 d gpio143_pins
ffff800081106260 d gpio142_pins
ffff800081106268 d gpio141_pins
ffff800081106270 d gpio140_pins
ffff800081106278 d gpio139_pins
ffff800081106280 d gpio138_pins
ffff800081106288 d gpio137_pins
ffff800081106290 d gpio136_pins
ffff800081106298 d gpio135_pins
ffff8000811062a0 d gpio134_pins
ffff8000811062a8 d gpio133_pins
ffff8000811062b0 d gpio132_pins
ffff8000811062b8 d gpio131_pins
ffff8000811062c0 d gpio130_pins
ffff8000811062c8 d gpio129_pins
ffff8000811062d0 d gpio128_pins
ffff8000811062d8 d gpio127_pins
ffff8000811062e0 d gpio126_pins
ffff8000811062e8 d gpio125_pins
ffff8000811062f0 d gpio124_pins
ffff8000811062f8 d gpio123_pins
ffff800081106300 d gpio122_pins
ffff800081106308 d gpio121_pins
ffff800081106310 d gpio120_pins
ffff800081106318 d gpio119_pins
ffff800081106320 d gpio118_pins
ffff800081106328 d gpio117_pins
ffff800081106330 d gpio116_pins
ffff800081106338 d gpio115_pins
ffff800081106340 d gpio114_pins
ffff800081106348 d gpio113_pins
ffff800081106350 d gpio112_pins
ffff800081106358 d gpio111_pins
ffff800081106360 d gpio110_pins
ffff800081106368 d gpio109_pins
ffff800081106370 d gpio108_pins
ffff800081106378 d gpio107_pins
ffff800081106380 d gpio106_pins
ffff800081106388 d gpio105_pins
ffff800081106390 d gpio104_pins
ffff800081106398 d gpio103_pins
ffff8000811063a0 d gpio102_pins
ffff8000811063a8 d gpio101_pins
ffff8000811063b0 d gpio100_pins
ffff8000811063b8 d gpio99_pins
ffff8000811063c0 d gpio98_pins
ffff8000811063c8 d gpio97_pins
ffff8000811063d0 d gpio96_pins
ffff8000811063d8 d gpio95_pins
ffff8000811063e0 d gpio94_pins
ffff8000811063e8 d gpio93_pins
ffff8000811063f0 d gpio92_pins
ffff8000811063f8 d gpio91_pins
ffff800081106400 d gpio90_pins
ffff800081106408 d gpio89_pins
ffff800081106410 d gpio88_pins
ffff800081106418 d gpio87_pins
ffff800081106420 d gpio86_pins
ffff800081106428 d gpio85_pins
ffff800081106430 d gpio84_pins
ffff800081106438 d gpio83_pins
ffff800081106440 d gpio82_pins
ffff800081106448 d gpio81_pins
ffff800081106450 d gpio80_pins
ffff800081106458 d gpio79_pins
ffff800081106460 d gpio78_pins
ffff800081106468 d gpio77_pins
ffff800081106470 d gpio76_pins
ffff800081106478 d gpio75_pins
ffff800081106480 d gpio74_pins
ffff800081106488 d gpio73_pins
ffff800081106490 d gpio72_pins
ffff800081106498 d gpio71_pins
ffff8000811064a0 d gpio70_pins
ffff8000811064a8 d gpio69_pins
ffff8000811064b0 d gpio68_pins
ffff8000811064b8 d gpio67_pins
ffff8000811064c0 d gpio66_pins
ffff8000811064c8 d gpio65_pins
ffff8000811064d0 d gpio64_pins
ffff8000811064d8 d gpio63_pins
ffff8000811064e0 d gpio62_pins
ffff8000811064e8 d gpio61_pins
ffff8000811064f0 d gpio60_pins
ffff8000811064f8 d gpio59_pins
ffff800081106500 d gpio58_pins
ffff800081106508 d gpio57_pins
ffff800081106510 d gpio56_pins
ffff800081106518 d gpio55_pins
ffff800081106520 d gpio54_pins
ffff800081106528 d gpio53_pins
ffff800081106530 d gpio52_pins
ffff800081106538 d gpio51_pins
ffff800081106540 d gpio50_pins
ffff800081106548 d gpio49_pins
ffff800081106550 d gpio48_pins
ffff800081106558 d gpio47_pins
ffff800081106560 d gpio46_pins
ffff800081106568 d gpio45_pins
ffff800081106570 d gpio44_pins
ffff800081106578 d gpio43_pins
ffff800081106580 d gpio42_pins
ffff800081106588 d gpio41_pins
ffff800081106590 d gpio40_pins
ffff800081106598 d gpio39_pins
ffff8000811065a0 d gpio38_pins
ffff8000811065a8 d gpio37_pins
ffff8000811065b0 d gpio36_pins
ffff8000811065b8 d gpio35_pins
ffff8000811065c0 d gpio34_pins
ffff8000811065c8 d gpio33_pins
ffff8000811065d0 d gpio32_pins
ffff8000811065d8 d gpio31_pins
ffff8000811065e0 d gpio30_pins
ffff8000811065e8 d gpio29_pins
ffff8000811065f0 d gpio28_pins
ffff8000811065f8 d gpio27_pins
ffff800081106600 d gpio26_pins
ffff800081106608 d gpio25_pins
ffff800081106610 d gpio24_pins
ffff800081106618 d gpio23_pins
ffff800081106620 d gpio22_pins
ffff800081106628 d gpio21_pins
ffff800081106630 d gpio20_pins
ffff800081106638 d gpio19_pins
ffff800081106640 d gpio18_pins
ffff800081106648 d gpio17_pins
ffff800081106650 d gpio16_pins
ffff800081106658 d gpio15_pins
ffff800081106660 d gpio14_pins
ffff800081106668 d gpio13_pins
ffff800081106670 d gpio12_pins
ffff800081106678 d gpio11_pins
ffff800081106680 d gpio10_pins
ffff800081106688 d gpio9_pins
ffff800081106690 d gpio8_pins
ffff800081106698 d gpio7_pins
ffff8000811066a0 d gpio6_pins
ffff8000811066a8 d gpio5_pins
ffff8000811066b0 d gpio4_pins
ffff8000811066b8 d gpio3_pins
ffff8000811066c0 d gpio2_pins
ffff8000811066c8 d gpio1_pins
ffff8000811066d0 d gpio0_pins
ffff8000811066d8 d sdm845_pins
ffff800081107548 d cfg_params
ffff800081107598 d samsung_pctrl_ops
ffff8000811075c8 d samsung_pinmux_ops
ffff800081107620 d samsung_pinconf_ops
ffff800081107660 d reg_names
ffff800081107690 d __func__.0
ffff8000811076a8 d __func__.1
ffff8000811076c0 d samsung_pinctrl_pm_ops
ffff800081107778 d samsung_pinctrl_dt_match
ffff800081108330 d exynos_eint_irqd_ops
ffff800081108380 d exynos_wkup_irq_ids
ffff8000811089c0 d __func__.0
ffff8000811089e0 d __func__.1
ffff8000811089f8 d __func__.2
ffff800081108a10 d __func__.3
ffff800081108a30 d __func__.4
ffff800081108a48 d __func__.5
ffff800081108a60 d __func__.6
ffff800081108a88 d gs101_pin_hsi2
ffff800081108b30 d gs101_pin_hsi1
ffff800081108ba0 d gs101_pin_peric1
ffff800081108d60 d gs101_pin_peric0
ffff8000811091c0 d gs101_pin_gsactrl
ffff8000811091f8 d gs101_pin_gsacore
ffff8000811092a0 d gs101_pin_far_alive
ffff800081109380 d gs101_pin_alive
ffff800081109540 d exynosautov920_pin_ctrl
ffff800081109740 d exynosautov920_pin_banks7
ffff800081109938 d exynosautov920_pin_banks6
ffff800081109b68 d exynosautov920_pin_banks5
ffff800081109ba0 d exynosautov920_pin_banks4
ffff800081109c80 d exynosautov920_pin_banks3
ffff800081109cb8 d exynosautov920_pin_banks2
ffff800081109d28 d exynosautov920_pin_banks1
ffff800081109eb0 d exynosautov920_pin_banks0
ffff800081109f58 d exynos5433_fsys_retention_regs
ffff800081109f68 d exynos5433_audio_retention_regs
ffff800081109f70 d exynos5433_retention_regs
ffff800081109f98 d exynos2200_pin_ctrl
ffff80008110a1d8 d artpec_bank_type_off
ffff80008110a1e8 d exynos8895_bank_type_off
ffff80008110a1f8 d exynos850_bank_type_alive
ffff80008110a208 d exynos850_bank_type_off
ffff80008110a218 d exynos7870_bank_type_alive
ffff80008110a228 d exynos5433_bank_type_alive
ffff80008110a238 d exynos5433_bank_type_off
ffff80008110a248 d bank_type_alive
ffff80008110a258 d bank_type_off
ffff80008110a268 d sunxi_pinctrl_irq_domain_ops
ffff80008110a2b8 d sunxi_pconf_ops
ffff80008110a2f8 d sunxi_pctrl_ops
ffff80008110a328 d sunxi_pmx_ops
ffff80008110a380 d __func__.0
ffff80008110a3a0 d a64_pinctrl_data
ffff80008110a3c8 d a64_pinctrl_match
ffff80008110a558 d a64_pins
ffff80008110b570 d sun50i_a64_r_pinctrl_data
ffff80008110b598 d sun50i_a64_r_pinctrl_match
ffff80008110b728 d sun50i_a64_r_pins
ffff80008110b930 d a100_pinctrl_data
ffff80008110b958 d a100_pinctrl_match
ffff80008110bae8 d a100_irq_bank_map
ffff80008110bb08 d a100_pins
ffff80008110cb20 d a100_r_pinctrl_data
ffff80008110cb48 d a100_r_pinctrl_match
ffff80008110ccd8 d a100_r_pins
ffff80008110ceb8 d sun8i_h3_r_pinctrl_data
ffff80008110cee0 d sun8i_h3_r_pinctrl_match
ffff80008110d070 d sun8i_h3_r_pins
ffff80008110d250 d sun50i_h5_pinctrl_data_broken
ffff80008110d278 d sun50i_h5_pinctrl_data
ffff80008110d2a0 d sun50i_h5_pinctrl_match
ffff80008110d430 d sun50i_h5_pins
ffff80008110e2e0 d h6_pinctrl_data
ffff80008110e308 d h6_pinctrl_match
ffff80008110e498 d h6_irq_bank_map
ffff80008110e4a8 d h6_pins
ffff80008110f588 d sun50i_h6_r_pinctrl_data
ffff80008110f5b0 d sun50i_h6_r_pinctrl_match
ffff80008110f740 d sun50i_h6_r_pins
ffff80008110f9c0 d h616_pinctrl_data
ffff80008110f9e8 d h616_pinctrl_match
ffff80008110fb78 d h616_irq_bank_map
ffff80008110fb98 d h616_pins
ffff800081111100 d sun50i_h616_r_pinctrl_data
ffff800081111128 d sun50i_h616_r_pinctrl_match
ffff8000811112b8 d sun50i_h616_r_pins
ffff800081111308 d a523_irq_bank_muxes
ffff800081111318 d a523_nr_bank_pins
ffff800081111328 d a523_pinctrl_match
ffff8000811114b8 d a523_irq_bank_map
ffff8000811114e0 d a523_r_irq_bank_muxes
ffff8000811114f0 d a523_r_nr_bank_pins
ffff800081111500 d a523_r_pinctrl_match
ffff800081111690 d a523_r_irq_bank_map
ffff8000811116b8 d cfg_params
ffff8000811117c8 d tegra_pinctrl_ops
ffff8000811117f8 d tegra_pinmux_ops
ffff800081111850 d tegra_pinconf_ops
ffff800081111890 d __func__.0
ffff8000811118a8 D tegra_pinctrl_pm
ffff800081111960 d tegra124_pinctrl
ffff8000811119a0 d tegra124_pinctrl_of_match
ffff800081111b30 d tegra124_groups
ffff800081115530 d tegra124_functions
ffff8000811157e0 d mipi_pad_ctrl_dsi_b_pins
ffff800081115808 d drive_ao4_pins
ffff800081115810 d drive_sdio4_pins
ffff800081115818 d drive_hv0_pins
ffff800081115820 d drive_ao0_pins
ffff800081115828 d drive_ao3_pins
ffff800081115830 d drive_usb_vbus_en_pins
ffff800081115838 d drive_dap5_pins
ffff800081115848 d drive_at6_pins
ffff800081115870 d drive_cec_pins
ffff800081115878 d drive_dev3_pins
ffff800081115880 d drive_gpv_pins
ffff8000811158a0 d drive_uda_pins
ffff8000811158b0 d drive_owr_pins
ffff8000811158b8 d drive_gmh_pins
ffff8000811158c0 d drive_gmg_pins
ffff8000811158c8 d drive_gmf_pins
ffff8000811158d8 d drive_gme_pins
ffff8000811158f0 d drive_gma_pins
ffff800081115918 d drive_ddc_pins
ffff800081115920 d drive_sdio1_pins
ffff800081115938 d drive_uart3_pins
ffff800081115948 d drive_uart2_pins
ffff800081115958 d drive_uab_pins
ffff800081115970 d drive_uaa_pins
ffff800081115980 d drive_spi_pins
ffff8000811159a8 d drive_sdio3_pins
ffff8000811159c8 d drive_dbg_pins
ffff8000811159f0 d drive_dap4_pins
ffff800081115a00 d drive_dap3_pins
ffff800081115a10 d drive_dap2_pins
ffff800081115a20 d drive_dap1_pins
ffff800081115a30 d drive_cdev2_pins
ffff800081115a38 d drive_cdev1_pins
ffff800081115a40 d drive_at5_pins
ffff800081115a48 d drive_at4_pins
ffff800081115a60 d drive_at3_pins
ffff800081115a68 d drive_at2_pins
ffff800081115aa8 d drive_at1_pins
ffff800081115ab8 d drive_ao2_pins
ffff800081115b18 d drive_ao1_pins
ffff800081115b40 d jtag_rtck_pins
ffff800081115b48 d clk_32k_in_pins
ffff800081115b50 d owr_pins
ffff800081115b58 d reset_out_n_pins
ffff800081115b60 d gmi_clk_lb_pins
ffff800081115b68 d pwr_int_n_pins
ffff800081115b70 d cpu_pwr_req_pins
ffff800081115b78 d core_pwr_req_pins
ffff800081115b80 d pff2_pins
ffff800081115b88 d usb_vbus_en2_pff1_pins
ffff800081115b90 d dp_hpd_pff0_pins
ffff800081115b98 d sdmmc3_clk_lb_in_pee5_pins
ffff800081115ba0 d sdmmc3_clk_lb_out_pee4_pins
ffff800081115ba8 d hdmi_cec_pee3_pins
ffff800081115bb0 d dap_mclk1_req_pee2_pins
ffff800081115bb8 d clk3_req_pee1_pins
ffff800081115bc0 d clk3_out_pee0_pins
ffff800081115bc8 d pex_l1_clkreq_n_pdd6_pins
ffff800081115bd0 d pex_l1_rst_n_pdd5_pins
ffff800081115bd8 d pex_wake_n_pdd3_pins
ffff800081115be0 d pex_l0_clkreq_n_pdd2_pins
ffff800081115be8 d pex_l0_rst_n_pdd1_pins
ffff800081115bf0 d clk2_req_pcc5_pins
ffff800081115bf8 d sdmmc4_clk_pcc4_pins
ffff800081115c00 d pcc2_pins
ffff800081115c08 d pcc1_pins
ffff800081115c10 d cam_mclk_pcc0_pins
ffff800081115c18 d pbb7_pins
ffff800081115c20 d pbb6_pins
ffff800081115c28 d pbb5_pins
ffff800081115c30 d pbb4_pins
ffff800081115c38 d pbb3_pins
ffff800081115c40 d cam_i2c_sda_pbb2_pins
ffff800081115c48 d cam_i2c_scl_pbb1_pins
ffff800081115c50 d pbb0_pins
ffff800081115c58 d sdmmc4_dat7_paa7_pins
ffff800081115c60 d sdmmc4_dat6_paa6_pins
ffff800081115c68 d sdmmc4_dat5_paa5_pins
ffff800081115c70 d sdmmc4_dat4_paa4_pins
ffff800081115c78 d sdmmc4_dat3_paa3_pins
ffff800081115c80 d sdmmc4_dat2_paa2_pins
ffff800081115c88 d sdmmc4_dat1_paa1_pins
ffff800081115c90 d sdmmc4_dat0_paa0_pins
ffff800081115c98 d pwr_i2c_sda_pz7_pins
ffff800081115ca0 d pwr_i2c_scl_pz6_pins
ffff800081115ca8 d sdmmc1_cmd_pz1_pins
ffff800081115cb0 d sdmmc1_clk_pz0_pins
ffff800081115cb8 d sdmmc1_dat0_py7_pins
ffff800081115cc0 d sdmmc1_dat1_py6_pins
ffff800081115cc8 d sdmmc1_dat2_py5_pins
ffff800081115cd0 d sdmmc1_dat3_py4_pins
ffff800081115cd8 d ulpi_stp_py3_pins
ffff800081115ce0 d ulpi_nxt_py2_pins
ffff800081115ce8 d ulpi_dir_py1_pins
ffff800081115cf0 d ulpi_clk_py0_pins
ffff800081115cf8 d gpio_x7_aud_px7_pins
ffff800081115d00 d gpio_x6_aud_px6_pins
ffff800081115d08 d gpio_x5_aud_px5_pins
ffff800081115d10 d gpio_x4_aud_px4_pins
ffff800081115d18 d gpio_x3_aud_px3_pins
ffff800081115d20 d dvfs_clk_px2_pins
ffff800081115d28 d gpio_x1_aud_px1_pins
ffff800081115d30 d dvfs_pwm_px0_pins
ffff800081115d38 d uart3_rxd_pw7_pins
ffff800081115d40 d uart3_txd_pw6_pins
ffff800081115d48 d clk2_out_pw5_pins
ffff800081115d50 d dap_mclk1_pw4_pins
ffff800081115d58 d gpio_w3_aud_pw3_pins
ffff800081115d60 d gpio_w2_aud_pw2_pins
ffff800081115d68 d ddc_sda_pv5_pins
ffff800081115d70 d ddc_scl_pv4_pins
ffff800081115d78 d sdmmc1_wp_n_pv3_pins
ffff800081115d80 d sdmmc3_cd_n_pv2_pins
ffff800081115d88 d pv1_pins
ffff800081115d90 d pv0_pins
ffff800081115d98 d pu6_pins
ffff800081115da0 d pu5_pins
ffff800081115da8 d pu4_pins
ffff800081115db0 d pu3_pins
ffff800081115db8 d pu2_pins
ffff800081115dc0 d pu1_pins
ffff800081115dc8 d pu0_pins
ffff800081115dd0 d sdmmc4_cmd_pt7_pins
ffff800081115dd8 d gen2_i2c_sda_pt6_pins
ffff800081115de0 d gen2_i2c_scl_pt5_pins
ffff800081115de8 d kb_row17_pt1_pins
ffff800081115df0 d kb_row16_pt0_pins
ffff800081115df8 d kb_row15_ps7_pins
ffff800081115e00 d kb_row14_ps6_pins
ffff800081115e08 d kb_row13_ps5_pins
ffff800081115e10 d kb_row12_ps4_pins
ffff800081115e18 d kb_row11_ps3_pins
ffff800081115e20 d kb_row10_ps2_pins
ffff800081115e28 d kb_row9_ps1_pins
ffff800081115e30 d kb_row8_ps0_pins
ffff800081115e38 d kb_row7_pr7_pins
ffff800081115e40 d kb_row6_pr6_pins
ffff800081115e48 d kb_row5_pr5_pins
ffff800081115e50 d kb_row4_pr4_pins
ffff800081115e58 d kb_row3_pr3_pins
ffff800081115e60 d kb_row2_pr2_pins
ffff800081115e68 d kb_row1_pr1_pins
ffff800081115e70 d kb_row0_pr0_pins
ffff800081115e78 d kb_col7_pq7_pins
ffff800081115e80 d kb_col6_pq6_pins
ffff800081115e88 d kb_col5_pq5_pins
ffff800081115e90 d kb_col4_pq4_pins
ffff800081115e98 d kb_col3_pq3_pins
ffff800081115ea0 d kb_col2_pq2_pins
ffff800081115ea8 d kb_col1_pq1_pins
ffff800081115eb0 d kb_col0_pq0_pins
ffff800081115eb8 d dap4_sclk_pp7_pins
ffff800081115ec0 d dap4_dout_pp6_pins
ffff800081115ec8 d dap4_din_pp5_pins
ffff800081115ed0 d dap4_fs_pp4_pins
ffff800081115ed8 d dap3_sclk_pp3_pins
ffff800081115ee0 d dap3_dout_pp2_pins
ffff800081115ee8 d dap3_din_pp1_pins
ffff800081115ef0 d dap3_fs_pp0_pins
ffff800081115ef8 d ulpi_data6_po7_pins
ffff800081115f00 d ulpi_data5_po6_pins
ffff800081115f08 d ulpi_data4_po5_pins
ffff800081115f10 d ulpi_data3_po4_pins
ffff800081115f18 d ulpi_data2_po3_pins
ffff800081115f20 d ulpi_data1_po2_pins
ffff800081115f28 d ulpi_data0_po1_pins
ffff800081115f30 d ulpi_data7_po0_pins
ffff800081115f38 d hdmi_int_pn7_pins
ffff800081115f40 d usb_vbus_en1_pn5_pins
ffff800081115f48 d usb_vbus_en0_pn4_pins
ffff800081115f50 d dap1_sclk_pn3_pins
ffff800081115f58 d dap1_dout_pn2_pins
ffff800081115f60 d dap1_din_pn1_pins
ffff800081115f68 d dap1_fs_pn0_pins
ffff800081115f70 d pk7_pins
ffff800081115f78 d spdif_in_pk6_pins
ffff800081115f80 d spdif_out_pk5_pins
ffff800081115f88 d pk4_pins
ffff800081115f90 d pk3_pins
ffff800081115f98 d pk2_pins
ffff800081115fa0 d pk1_pins
ffff800081115fa8 d pk0_pins
ffff800081115fb0 d pj7_pins
ffff800081115fb8 d uart2_rts_n_pj6_pins
ffff800081115fc0 d uart2_cts_n_pj5_pins
ffff800081115fc8 d pj2_pins
ffff800081115fd0 d pj0_pins
ffff800081115fd8 d pi7_pins
ffff800081115fe0 d pi6_pins
ffff800081115fe8 d pi5_pins
ffff800081115ff0 d pi4_pins
ffff800081115ff8 d pi3_pins
ffff800081116000 d pi2_pins
ffff800081116008 d pi1_pins
ffff800081116010 d pi0_pins
ffff800081116018 d ph7_pins
ffff800081116020 d ph6_pins
ffff800081116028 d ph5_pins
ffff800081116030 d ph4_pins
ffff800081116038 d ph3_pins
ffff800081116040 d ph2_pins
ffff800081116048 d ph1_pins
ffff800081116050 d ph0_pins
ffff800081116058 d pg7_pins
ffff800081116060 d pg6_pins
ffff800081116068 d pg5_pins
ffff800081116070 d pg4_pins
ffff800081116078 d pg3_pins
ffff800081116080 d pg2_pins
ffff800081116088 d pg1_pins
ffff800081116090 d pg0_pins
ffff800081116098 d pc7_pins
ffff8000811160a0 d gen1_i2c_sda_pc5_pins
ffff8000811160a8 d gen1_i2c_scl_pc4_pins
ffff8000811160b0 d uart2_rxd_pc3_pins
ffff8000811160b8 d uart2_txd_pc2_pins
ffff8000811160c0 d uart3_rts_n_pc0_pins
ffff8000811160c8 d sdmmc3_dat0_pb7_pins
ffff8000811160d0 d sdmmc3_dat1_pb6_pins
ffff8000811160d8 d sdmmc3_dat2_pb5_pins
ffff8000811160e0 d sdmmc3_dat3_pb4_pins
ffff8000811160e8 d pb1_pins
ffff8000811160f0 d pb0_pins
ffff8000811160f8 d sdmmc3_cmd_pa7_pins
ffff800081116100 d sdmmc3_clk_pa6_pins
ffff800081116108 d dap2_dout_pa5_pins
ffff800081116110 d dap2_din_pa4_pins
ffff800081116118 d dap2_sclk_pa3_pins
ffff800081116120 d dap2_fs_pa2_pins
ffff800081116128 d uart3_cts_n_pa1_pins
ffff800081116130 d clk_32k_out_pa0_pins
ffff800081116138 d tegra124_pins
ffff800081117410 d tegra210_pinctrl
ffff800081117450 d tegra210_pinctrl_of_match
ffff8000811175e0 d tegra210_groups
ffff80008111a4a0 d tegra210_functions
ffff80008111a6e8 d drive_sdmmc3_pins
ffff80008111a6e8 d drive_sdmmc4_pins
ffff80008111a700 d drive_sdmmc1_pins
ffff80008111a700 d drive_sdmmc2_pins
ffff80008111a718 d drive_pz5_pins
ffff80008111a720 d drive_pz4_pins
ffff80008111a728 d drive_pz3_pins
ffff80008111a730 d drive_pz2_pins
ffff80008111a738 d drive_pz1_pins
ffff80008111a740 d drive_pz0_pins
ffff80008111a748 d drive_pl1_pins
ffff80008111a750 d drive_pl0_pins
ffff80008111a758 d drive_pk7_pins
ffff80008111a760 d drive_pk6_pins
ffff80008111a768 d drive_pk5_pins
ffff80008111a770 d drive_pk4_pins
ffff80008111a778 d drive_pk3_pins
ffff80008111a780 d drive_pk2_pins
ffff80008111a788 d drive_pk1_pins
ffff80008111a790 d drive_pk0_pins
ffff80008111a798 d drive_ph6_pins
ffff80008111a7a0 d drive_pe7_pins
ffff80008111a7a8 d drive_pe6_pins
ffff80008111a7b0 d drive_pcc7_pins
ffff80008111a7b8 d drive_pa6_pins
ffff80008111a7c0 d shutdown_pins
ffff80008111a7c8 d clk_req_pins
ffff80008111a7d0 d batt_bcl_pins
ffff80008111a7d8 d jtag_rtck_pins
ffff80008111a7e0 d clk_32k_in_pins
ffff80008111a7e8 d pwr_int_n_pins
ffff80008111a7f0 d cpu_pwr_req_pins
ffff80008111a7f8 d core_pwr_req_pins
ffff80008111a800 d qspi_io3_pee5_pins
ffff80008111a808 d qspi_io2_pee4_pins
ffff80008111a810 d qspi_io1_pee3_pins
ffff80008111a818 d qspi_io0_pee2_pins
ffff80008111a820 d qspi_cs_n_pee1_pins
ffff80008111a828 d qspi_sck_pee0_pins
ffff80008111a830 d spi2_cs1_pdd0_pins
ffff80008111a838 d pcc7_pins
ffff80008111a840 d dp_hpd0_pcc6_pins
ffff80008111a848 d usb_vbus_en1_pcc5_pins
ffff80008111a850 d usb_vbus_en0_pcc4_pins
ffff80008111a858 d spdif_in_pcc3_pins
ffff80008111a860 d spdif_out_pcc2_pins
ffff80008111a868 d hdmi_int_dp_hpd_pcc1_pins
ffff80008111a870 d hdmi_cec_pcc0_pins
ffff80008111a878 d gpio_x3_aud_pbb4_pins
ffff80008111a880 d gpio_x1_aud_pbb3_pins
ffff80008111a888 d dvfs_clk_pbb2_pins
ffff80008111a890 d dvfs_pwm_pbb1_pins
ffff80008111a898 d aud_mclk_pbb0_pins
ffff80008111a8a0 d dap2_dout_paa3_pins
ffff80008111a8a8 d dap2_din_paa2_pins
ffff80008111a8b0 d dap2_sclk_paa1_pins
ffff80008111a8b8 d dap2_fs_paa0_pins
ffff80008111a8c0 d pz5_pins
ffff80008111a8c8 d pz4_pins
ffff80008111a8d0 d pz3_pins
ffff80008111a8d8 d pz2_pins
ffff80008111a8e0 d pz1_pins
ffff80008111a8e8 d pz0_pins
ffff80008111a8f0 d clk_32k_out_py5_pins
ffff80008111a8f8 d pwr_i2c_sda_py4_pins
ffff80008111a900 d pwr_i2c_scl_py3_pins
ffff80008111a908 d lcd_te_py2_pins
ffff80008111a910 d button_home_py1_pins
ffff80008111a918 d button_slide_sw_py0_pins
ffff80008111a920 d button_vol_down_px7_pins
ffff80008111a928 d button_vol_up_px6_pins
ffff80008111a930 d button_power_on_px5_pins
ffff80008111a938 d temp_alert_px4_pins
ffff80008111a940 d als_prox_int_px3_pins
ffff80008111a948 d motion_int_px2_pins
ffff80008111a950 d touch_int_px1_pins
ffff80008111a958 d modem_wake_ap_px0_pins
ffff80008111a960 d touch_clk_pv7_pins
ffff80008111a968 d touch_rst_pv6_pins
ffff80008111a970 d ap_ready_pv5_pins
ffff80008111a978 d lcd_gpio2_pv4_pins
ffff80008111a980 d lcd_gpio1_pv3_pins
ffff80008111a988 d lcd_rst_pv2_pins
ffff80008111a990 d lcd_bl_en_pv1_pins
ffff80008111a998 d lcd_bl_pwm_pv0_pins
ffff80008111a9a0 d uart1_cts_pu3_pins
ffff80008111a9a8 d uart1_rts_pu2_pins
ffff80008111a9b0 d uart1_rx_pu1_pins
ffff80008111a9b8 d uart1_tx_pu0_pins
ffff80008111a9c0 d cam1_strobe_pt1_pins
ffff80008111a9c8 d cam2_pwdn_pt0_pins
ffff80008111a9d0 d cam1_pwdn_ps7_pins
ffff80008111a9d8 d cam_flash_en_ps6_pins
ffff80008111a9e0 d cam_af_en_ps5_pins
ffff80008111a9e8 d cam_rst_ps4_pins
ffff80008111a9f0 d cam_i2c_sda_ps3_pins
ffff80008111a9f8 d cam_i2c_scl_ps2_pins
ffff80008111aa00 d cam2_mclk_ps1_pins
ffff80008111aa08 d cam1_mclk_ps0_pins
ffff80008111aa10 d sdmmc3_dat0_pp5_pins
ffff80008111aa18 d sdmmc3_dat1_pp4_pins
ffff80008111aa20 d sdmmc3_dat2_pp3_pins
ffff80008111aa28 d sdmmc3_dat3_pp2_pins
ffff80008111aa30 d sdmmc3_cmd_pp1_pins
ffff80008111aa38 d sdmmc3_clk_pp0_pins
ffff80008111aa40 d sdmmc1_dat0_pm5_pins
ffff80008111aa48 d sdmmc1_dat1_pm4_pins
ffff80008111aa50 d sdmmc1_dat2_pm3_pins
ffff80008111aa58 d sdmmc1_dat3_pm2_pins
ffff80008111aa60 d sdmmc1_cmd_pm1_pins
ffff80008111aa68 d sdmmc1_clk_pm0_pins
ffff80008111aa70 d pl1_pins
ffff80008111aa78 d pl0_pins
ffff80008111aa80 d pk7_pins
ffff80008111aa88 d pk6_pins
ffff80008111aa90 d pk5_pins
ffff80008111aa98 d pk4_pins
ffff80008111aaa0 d pk3_pins
ffff80008111aaa8 d pk2_pins
ffff80008111aab0 d pk1_pins
ffff80008111aab8 d pk0_pins
ffff80008111aac0 d dap4_sclk_pj7_pins
ffff80008111aac8 d dap4_dout_pj6_pins
ffff80008111aad0 d dap4_din_pj5_pins
ffff80008111aad8 d dap4_fs_pj4_pins
ffff80008111aae0 d gen2_i2c_sda_pj3_pins
ffff80008111aae8 d gen2_i2c_scl_pj2_pins
ffff80008111aaf0 d gen1_i2c_scl_pj1_pins
ffff80008111aaf8 d gen1_i2c_sda_pj0_pins
ffff80008111ab00 d uart4_cts_pi7_pins
ffff80008111ab08 d uart4_rts_pi6_pins
ffff80008111ab10 d uart4_rx_pi5_pins
ffff80008111ab18 d uart4_tx_pi4_pins
ffff80008111ab20 d gps_rst_pi3_pins
ffff80008111ab28 d gps_en_pi2_pins
ffff80008111ab30 d nfc_int_pi1_pins
ffff80008111ab38 d nfc_en_pi0_pins
ffff80008111ab40 d ap_wake_nfc_ph7_pins
ffff80008111ab48 d ph6_pins
ffff80008111ab50 d bt_wake_ap_ph5_pins
ffff80008111ab58 d bt_rst_ph4_pins
ffff80008111ab60 d ap_wake_bt_ph3_pins
ffff80008111ab68 d wifi_wake_ap_ph2_pins
ffff80008111ab70 d wifi_rst_ph1_pins
ffff80008111ab78 d wifi_en_ph0_pins
ffff80008111ab80 d uart2_cts_pg3_pins
ffff80008111ab88 d uart2_rts_pg2_pins
ffff80008111ab90 d uart2_rx_pg1_pins
ffff80008111ab98 d uart2_tx_pg0_pins
ffff80008111aba0 d gen3_i2c_sda_pf1_pins
ffff80008111aba8 d gen3_i2c_scl_pf0_pins
ffff80008111abb0 d pe7_pins
ffff80008111abb8 d pe6_pins
ffff80008111abc0 d dmic3_dat_pe5_pins
ffff80008111abc8 d dmic3_clk_pe4_pins
ffff80008111abd0 d dmic2_dat_pe3_pins
ffff80008111abd8 d dmic2_clk_pe2_pins
ffff80008111abe0 d dmic1_dat_pe1_pins
ffff80008111abe8 d dmic1_clk_pe0_pins
ffff80008111abf0 d uart3_cts_pd4_pins
ffff80008111abf8 d uart3_rts_pd3_pins
ffff80008111ac00 d uart3_rx_pd2_pins
ffff80008111ac08 d uart3_tx_pd1_pins
ffff80008111ac10 d spi4_miso_pd0_pins
ffff80008111ac18 d spi4_mosi_pc7_pins
ffff80008111ac20 d spi4_cs0_pc6_pins
ffff80008111ac28 d spi4_sck_pc5_pins
ffff80008111ac30 d spi1_cs1_pc4_pins
ffff80008111ac38 d spi1_cs0_pc3_pins
ffff80008111ac40 d spi1_sck_pc2_pins
ffff80008111ac48 d spi1_miso_pc1_pins
ffff80008111ac50 d spi1_mosi_pc0_pins
ffff80008111ac58 d spi2_cs0_pb7_pins
ffff80008111ac60 d spi2_sck_pb6_pins
ffff80008111ac68 d spi2_miso_pb5_pins
ffff80008111ac70 d spi2_mosi_pb4_pins
ffff80008111ac78 d dap1_sclk_pb3_pins
ffff80008111ac80 d dap1_dout_pb2_pins
ffff80008111ac88 d dap1_din_pb1_pins
ffff80008111ac90 d dap1_fs_pb0_pins
ffff80008111ac98 d pa6_pins
ffff80008111aca0 d sata_led_active_pa5_pins
ffff80008111aca8 d pex_l1_clkreq_n_pa4_pins
ffff80008111acb0 d pex_l1_rst_n_pa3_pins
ffff80008111acb8 d pex_wake_n_pa2_pins
ffff80008111acc0 d pex_l0_clkreq_n_pa1_pins
ffff80008111acc8 d pex_l0_rst_n_pa0_pins
ffff80008111acd0 d tegra210_pins
ffff80008111bc00 d tegra194_pinctrl_of_match
ffff80008111be58 d tegra194_pinctrl_aon
ffff80008111be98 d tegra194_aon_groups
ffff80008111c718 d tegra194_aon_pins
ffff80008111ca60 d tegra194_pinctrl
ffff80008111caa0 d tegra194_groups
ffff80008111f8e0 d tegra194_functions
ffff80008111fb78 d clk_32k_in_pins
ffff80008111fb80 d soc_pwr_req_pins
ffff80008111fb88 d pmu_int_n_pins
ffff80008111fb90 d shutdown_n_pins
ffff80008111fb98 d qspi_comp_pins
ffff80008111fba0 d eqos_comp_pins
ffff80008111fba8 d sdmmc3_comp_pins
ffff80008111fbb0 d sdmmc1_comp_pins
ffff80008111fbb8 d sdmmc4_dat0_pins
ffff80008111fbc0 d sdmmc4_dat1_pins
ffff80008111fbc8 d sdmmc4_dat2_pins
ffff80008111fbd0 d sdmmc4_dat3_pins
ffff80008111fbd8 d sdmmc4_dat4_pins
ffff80008111fbe0 d sdmmc4_dat5_pins
ffff80008111fbe8 d sdmmc4_dat6_pins
ffff80008111fbf0 d sdmmc4_dat7_pins
ffff80008111fbf8 d sdmmc4_dqs_pins
ffff80008111fc00 d sdmmc4_cmd_pins
ffff80008111fc08 d sdmmc4_clk_pins
ffff80008111fc10 d directdc_comp_pins
ffff80008111fc18 d pex_l5_rst_n_pgg1_pins
ffff80008111fc20 d pex_l5_clkreq_n_pgg0_pins
ffff80008111fc28 d ufs0_rst_pff1_pins
ffff80008111fc30 d ufs0_ref_clk_pff0_pins
ffff80008111fc38 d pwr_i2c_sda_pee6_pins
ffff80008111fc40 d pwr_i2c_scl_pee5_pins
ffff80008111fc48 d power_on_pee4_pins
ffff80008111fc50 d batt_oc_pee3_pins
ffff80008111fc58 d ao_retention_n_pee2_pins
ffff80008111fc60 d vcomp_alert_pee1_pins
ffff80008111fc68 d safe_state_pee0_pins
ffff80008111fc70 d gen8_i2c_sda_pdd2_pins
ffff80008111fc78 d gen8_i2c_scl_pdd1_pins
ffff80008111fc80 d gen2_i2c_sda_pdd0_pins
ffff80008111fc88 d gen2_i2c_scl_pcc7_pins
ffff80008111fc90 d uart3_rx_pcc6_pins
ffff80008111fc98 d uart3_tx_pcc5_pins
ffff80008111fca0 d touch_clk_pcc4_pins
ffff80008111fca8 d spi2_cs0_pcc3_pins
ffff80008111fcb0 d spi2_mosi_pcc2_pins
ffff80008111fcb8 d spi2_miso_pcc1_pins
ffff80008111fcc0 d spi2_sck_pcc0_pins
ffff80008111fcc8 d can1_err_pbb3_pins
ffff80008111fcd0 d can1_wake_pbb2_pins
ffff80008111fcd8 d can1_en_pbb1_pins
ffff80008111fce0 d can1_stb_pbb0_pins
ffff80008111fce8 d can0_err_paa7_pins
ffff80008111fcf0 d can0_wake_paa6_pins
ffff80008111fcf8 d can0_en_paa5_pins
ffff80008111fd00 d can0_stb_paa4_pins
ffff80008111fd08 d can0_din_paa3_pins
ffff80008111fd10 d can0_dout_paa2_pins
ffff80008111fd18 d can1_din_paa1_pins
ffff80008111fd20 d can1_dout_paa0_pins
ffff80008111fd28 d spi1_cs1_pz7_pins
ffff80008111fd30 d spi1_cs0_pz6_pins
ffff80008111fd38 d spi1_mosi_pz5_pins
ffff80008111fd40 d spi1_miso_pz4_pins
ffff80008111fd48 d spi1_sck_pz3_pins
ffff80008111fd50 d usb_vbus_en1_pz2_pins
ffff80008111fd58 d usb_vbus_en0_pz1_pins
ffff80008111fd60 d uart5_cts_pz0_pins
ffff80008111fd68 d uart5_rts_py7_pins
ffff80008111fd70 d uart5_rx_py6_pins
ffff80008111fd78 d uart5_tx_py5_pins
ffff80008111fd80 d spi3_cs1_py4_pins
ffff80008111fd88 d spi3_cs0_py3_pins
ffff80008111fd90 d spi3_mosi_py2_pins
ffff80008111fd98 d spi3_miso_py1_pins
ffff80008111fda0 d spi3_sck_py0_pins
ffff80008111fda8 d uart2_cts_px7_pins
ffff80008111fdb0 d uart2_rts_px6_pins
ffff80008111fdb8 d uart2_rx_px5_pins
ffff80008111fdc0 d uart2_tx_px4_pins
ffff80008111fdc8 d gp_pwm3_px3_pins
ffff80008111fdd0 d gp_pwm2_px2_pins
ffff80008111fdd8 d cv_pwr_req_px1_pins
ffff80008111fde0 d gpu_pwr_req_px0_pins
ffff80008111fde8 d directdc1_out7_pw1_pins
ffff80008111fdf0 d directdc1_out6_pw0_pins
ffff80008111fdf8 d directdc1_out5_pv7_pins
ffff80008111fe00 d directdc1_out4_pv6_pins
ffff80008111fe08 d directdc1_out3_pv5_pins
ffff80008111fe10 d directdc1_out2_pv4_pins
ffff80008111fe18 d directdc1_out1_pv3_pins
ffff80008111fe20 d directdc1_out0_pv2_pins
ffff80008111fe28 d directdc1_in_pv1_pins
ffff80008111fe30 d directdc1_clk_pv0_pins
ffff80008111fe38 d dap5_fs_pu0_pins
ffff80008111fe40 d dap5_din_pt7_pins
ffff80008111fe48 d dap5_dout_pt6_pins
ffff80008111fe50 d dap5_sclk_pt5_pins
ffff80008111fe58 d dap3_fs_pt4_pins
ffff80008111fe60 d dap3_din_pt3_pins
ffff80008111fe68 d dap3_dout_pt2_pins
ffff80008111fe70 d dap3_sclk_pt1_pins
ffff80008111fe78 d soc_gpio33_pt0_pins
ffff80008111fe80 d soc_gpio32_ps7_pins
ffff80008111fe88 d soc_gpio31_ps6_pins
ffff80008111fe90 d soc_gpio30_ps5_pins
ffff80008111fe98 d aud_mclk_ps4_pins
ffff80008111fea0 d dap1_fs_ps3_pins
ffff80008111fea8 d dap1_din_ps2_pins
ffff80008111feb0 d dap1_dout_ps1_pins
ffff80008111feb8 d dap1_sclk_ps0_pins
ffff80008111fec0 d uart1_cts_pr5_pins
ffff80008111fec8 d uart1_rts_pr4_pins
ffff80008111fed0 d uart1_rx_pr3_pins
ffff80008111fed8 d uart1_tx_pr2_pins
ffff80008111fee0 d soc_gpio45_pr1_pins
ffff80008111fee8 d soc_gpio44_pr0_pins
ffff80008111fef0 d soc_gpio43_pq7_pins
ffff80008111fef8 d soc_gpio42_pq6_pins
ffff80008111ff00 d soc_gpio41_pq5_pins
ffff80008111ff08 d soc_gpio40_pq4_pins
ffff80008111ff10 d soc_gpio23_pq3_pins
ffff80008111ff18 d soc_gpio22_pq2_pins
ffff80008111ff20 d soc_gpio21_pq1_pins
ffff80008111ff28 d soc_gpio20_pq0_pins
ffff80008111ff30 d soc_gpio07_pp7_pins
ffff80008111ff38 d soc_gpio06_pp6_pins
ffff80008111ff40 d soc_gpio05_pp5_pins
ffff80008111ff48 d soc_gpio04_pp4_pins
ffff80008111ff50 d cam_i2c_sda_pp3_pins
ffff80008111ff58 d cam_i2c_scl_pp2_pins
ffff80008111ff60 d extperiph2_clk_pp1_pins
ffff80008111ff68 d extperiph1_clk_pp0_pins
ffff80008111ff70 d sdmmc3_dat3_po5_pins
ffff80008111ff78 d sdmmc3_dat2_po4_pins
ffff80008111ff80 d sdmmc3_dat1_po3_pins
ffff80008111ff88 d sdmmc3_dat0_po2_pins
ffff80008111ff90 d sdmmc3_cmd_po1_pins
ffff80008111ff98 d sdmmc3_clk_po0_pins
ffff80008111ffa0 d soc_gpio55_pn2_pins
ffff80008111ffa8 d soc_gpio54_pn1_pins
ffff80008111ffb0 d soc_gpio53_pn0_pins
ffff80008111ffb8 d soc_gpio52_pm7_pins
ffff80008111ffc0 d soc_gpio51_pm6_pins
ffff80008111ffc8 d soc_gpio50_pm5_pins
ffff80008111ffd0 d hdmi_cec_pm4_pins
ffff80008111ffd8 d dp_aux_ch3_hpd_pm3_pins
ffff80008111ffe0 d dp_aux_ch2_hpd_pm2_pins
ffff80008111ffe8 d dp_aux_ch1_hpd_pm1_pins
ffff80008111fff0 d dp_aux_ch0_hpd_pm0_pins
ffff80008111fff8 d sata_dev_slp_pl3_pins
ffff800081120000 d pex_wake_n_pl2_pins
ffff800081120008 d pex_l4_rst_n_pl1_pins
ffff800081120010 d pex_l4_clkreq_n_pl0_pins
ffff800081120018 d pex_l3_rst_n_pk7_pins
ffff800081120020 d pex_l3_clkreq_n_pk6_pins
ffff800081120028 d pex_l2_rst_n_pk5_pins
ffff800081120030 d pex_l2_clkreq_n_pk4_pins
ffff800081120038 d pex_l1_rst_n_pk3_pins
ffff800081120040 d pex_l1_clkreq_n_pk2_pins
ffff800081120048 d pex_l0_rst_n_pk1_pins
ffff800081120050 d pex_l0_clkreq_n_pk0_pins
ffff800081120058 d sdmmc1_dat3_pj5_pins
ffff800081120060 d sdmmc1_dat2_pj4_pins
ffff800081120068 d sdmmc1_dat1_pj3_pins
ffff800081120070 d sdmmc1_dat0_pj2_pins
ffff800081120078 d sdmmc1_cmd_pj1_pins
ffff800081120080 d sdmmc1_clk_pj0_pins
ffff800081120088 d gen1_i2c_sda_pi4_pins
ffff800081120090 d gen1_i2c_scl_pi3_pins
ffff800081120098 d dap2_fs_pi2_pins
ffff8000811200a0 d dap2_din_pi1_pins
ffff8000811200a8 d dap2_dout_pi0_pins
ffff8000811200b0 d dap2_sclk_ph7_pins
ffff8000811200b8 d uart4_cts_ph6_pins
ffff8000811200c0 d uart4_rts_ph5_pins
ffff8000811200c8 d uart4_rx_ph4_pins
ffff8000811200d0 d uart4_tx_ph3_pins
ffff8000811200d8 d soc_gpio14_ph2_pins
ffff8000811200e0 d soc_gpio13_ph1_pins
ffff8000811200e8 d soc_gpio12_ph0_pins
ffff8000811200f0 d soc_gpio11_pg7_pins
ffff8000811200f8 d soc_gpio10_pg6_pins
ffff800081120100 d soc_gpio09_pg5_pins
ffff800081120108 d soc_gpio08_pg4_pins
ffff800081120110 d soc_gpio03_pg3_pins
ffff800081120118 d soc_gpio02_pg2_pins
ffff800081120120 d soc_gpio01_pg1_pins
ffff800081120128 d soc_gpio00_pg0_pins
ffff800081120130 d eqos_sma_mdc_pf5_pins
ffff800081120138 d eqos_sma_mdio_pf4_pins
ffff800081120140 d eqos_rxc_pf3_pins
ffff800081120148 d eqos_rx_ctl_pf2_pins
ffff800081120150 d eqos_rd3_pf1_pins
ffff800081120158 d eqos_rd2_pf0_pins
ffff800081120160 d eqos_rd1_pe7_pins
ffff800081120168 d eqos_rd0_pe6_pins
ffff800081120170 d eqos_tx_ctl_pe5_pins
ffff800081120178 d eqos_td3_pe4_pins
ffff800081120180 d eqos_td2_pe3_pins
ffff800081120188 d eqos_td1_pe2_pins
ffff800081120190 d eqos_td0_pe1_pins
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ffff80008114d238 d comphy_mux_p
ffff80008114d248 d mmc_mux_p
ffff80008114d270 d hi6220_acpu_sc_gate_sep_clks
ffff80008114d2a8 d hisi_reset_ops
ffff80008114d2c8 d __func__.1
ffff80008114d2e0 d __func__.0
ffff80008114d300 d hi3660_stub_clk_of_match
ffff80008114d490 d hi3660_stub_clk_ops
ffff80008114d558 D mtk_clk_dummy_ops
ffff80008114d620 D cg_regs_dummy
ffff80008114d630 D mtk_pll_ops
ffff80008114d6f8 d __func__.0
ffff80008114d710 D mtk_pll_fenc_clr_set_ops
ffff80008114d7d8 D mtk_clk_gate_hwv_ops_setclr
ffff80008114d8a0 D mtk_clk_gate_hwv_ops_setclr_inv
ffff80008114d968 D mtk_clk_gate_ops_no_setclr_inv
ffff80008114da30 D mtk_clk_gate_ops_no_setclr
ffff80008114daf8 D mtk_clk_gate_ops_setclr_inv
ffff80008114dbc0 D mtk_clk_gate_ops_setclr
ffff80008114dc88 d mtk_ref2usb_tx_ops
ffff80008114dd50 d clk_cpumux_ops
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ffff80008114de38 d mtk_reset_ops_set_clr
ffff80008114de58 D mtk_mux_gate_hwv_fenc_clr_set_upd_ops
ffff80008114df20 D mtk_mux_gate_fenc_clr_set_upd_ops
ffff80008114dfe8 D mtk_mux_gate_clr_set_upd_ops
ffff80008114e0b0 D mtk_mux_clr_set_upd_ops
ffff80008114e178 d fhctl_offset_v1
ffff80008114e1a0 d fhctl_offset_v2
ffff80008114e1c8 d fhctl_ops
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ffff80008114e1e8 d __func__.0
ffff80008114e200 d mtk_pllfh_ops
ffff80008114e2c8 d ifr_clks
ffff80008114f288 d __func__.15
ffff80008114f2a0 d plls
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ffff80008114fac0 d __func__.17
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ffff80008114fb40 d top_divs
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ffff800081151260 d top_clks
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ffff800081151678 d of_match_clk_mt6765
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ffff8000811519b8 d ifr4_cg_regs
ffff8000811519c8 d ifr3_cg_regs
ffff8000811519d8 d ifr2_cg_regs
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ffff8000811519f8 d top1_cg_regs
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ffff800081151a38 d ulposc_parents
ffff800081151a60 d aes_fde_parents
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ffff800081151b10 d dxcc_parents
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ffff800081151b98 d aud_intbus_parents
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ffff800081151bd0 d msdc30_1_parents
ffff800081151c10 d msdc50_0_parents
ffff800081151c50 d msdc5hclk_parents
ffff800081151c70 d spi_parents
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ffff800081151ca0 d camtg_parents
ffff800081151cd8 d atb_parents
ffff800081151cf0 d mfg_parents
ffff800081151d10 d scp_parents
ffff800081151d48 d mm_parents
ffff800081151d88 d mem_parents
ffff800081151da0 d axi_parents
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ffff800081152c00 d plls
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ffff800081153580 d of_match_clk_mt6779_infra
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ffff800081153798 d of_match_clk_mt6779
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ffff800081153a00 d infra_clks
ffff8000811554c0 d infra3_cg_regs
ffff8000811554d0 d infra2_cg_regs
ffff8000811554e0 d infra1_cg_regs
ffff8000811554f0 d infra0_cg_regs
ffff800081155500 d i2s5_m_ck_parents
ffff800081155510 d i2s4_m_ck_parents
ffff800081155520 d i2s3_m_ck_parents
ffff800081155530 d i2s2_m_ck_parents
ffff800081155540 d i2s1_m_ck_parents
ffff800081155550 d i2s0_m_ck_parents
ffff800081155560 d top_muxes
ffff8000811569a0 d camtg5_parents
ffff8000811569e0 d audio_h_parents
ffff800081156a00 d pwm_parents
ffff800081156a10 d camtm_parents
ffff800081156a30 d vdec_parents
ffff800081156a88 d venc_parents
ffff800081156af0 d dpmaif_parents
ffff800081156b20 d adsp_parents
ffff800081156b58 d aud_2_parents
ffff800081156b68 d aud_1_parents
ffff800081156b78 d fufs_parents
ffff800081156b98 d faes_ufsfde_parents
ffff800081156bc8 d aud_engen2_parents
ffff800081156be8 d aud_engen1_parents
ffff800081156c08 d dxcc_parents
ffff800081156c28 d seninf2_parents
ffff800081156c68 d seninf1_parents
ffff800081156ca8 d seninf_parents
ffff800081156ce8 d i2c_parents
ffff800081156d00 d spm_parents
ffff800081156d18 d ssusb_top_xhci_parents
ffff800081156d38 d usb_top_parents
ffff800081156d58 d disppwm_parents
ffff800081156d80 d scam_parents
ffff800081156d90 d dpi0_parents
ffff800081156db8 d sspm_parents
ffff800081156de0 d atb_parents
ffff800081156df8 d fpwrap_ulposc_parents
ffff800081156e20 d aud_intbus_parents
ffff800081156e38 d audio_parents
ffff800081156e58 d msdc30_1_parents
ffff800081156e80 d msdc50_0_parents
ffff800081156eb0 d msdc50_hclk_parents
ffff800081156ec8 d spi_parents
ffff800081156ee8 d uart_parents
ffff800081156ef8 d camtg4_parents
ffff800081156f38 d camtg3_parents
ffff800081156f78 d camtg2_parents
ffff800081156fb8 d camtg_parents
ffff800081156ff8 d f52m_mfg_parents
ffff800081157018 d mfg_parents
ffff800081157038 d ipu_if_parents
ffff8000811570b8 d dsp3_parents
ffff800081157138 d dsp2_parents
ffff8000811571b8 d dsp1_parents
ffff800081157238 d dsp_parents
ffff8000811572b8 d ccu_parents
ffff800081157308 d cam_parents
ffff800081157358 d dpe_parents
ffff800081157398 d ipe_parents
ffff8000811573d8 d img_parents
ffff800081157418 d scp_parents
ffff800081157458 d mm_parents
ffff800081157488 d axi_parents
ffff8000811574a8 d plls
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ffff800081157af8 d of_match_clk_mt6795_apmixed
ffff800081157c88 d cpu_muxes
ffff800081157cf8 d infra_gates
ffff800081158078 d clk_rst_desc
ffff8000811580a0 d of_match_clk_mt6795_infracfg
ffff800081158230 d ca53_c1_parents
ffff800081158250 d ca53_c0_parents
ffff800081158270 d infra_cg_regs
ffff800081158280 d peri_clks
ffff800081158360 d peri_gates
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ffff800081158b08 d of_match_clk_mt6795_pericfg
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ffff800081158ca8 d peri_cg_regs
ffff800081158cb8 d of_match_clk_mt6795_topckgen
ffff800081158e48 d topck_desc
ffff800081158ed0 d top_muxes
ffff800081159a70 d top_divs
ffff80008115a600 d fixed_clks
ffff80008115a6a0 d venc_parents
ffff80008115a6f0 d vdec_parents
ffff80008115a740 d usb30_parents
ffff80008115a760 d usb20_parents
ffff80008115a778 d uart_parents
ffff80008115a788 d spi_parents
ffff80008115a7c0 d scp_parents
ffff80008115a7f0 d scam_parents
ffff80008115a810 d pwm_parents
ffff80008115a830 d pmicspi_parents
ffff80008115a870 d msdc30_3_parents
ffff80008115a8b0 d msdc30_2_parents
ffff80008115a8f0 d msdc30_1_parents
ffff80008115a930 d msdc50_0_parents
ffff80008115a990 d msdc50_0_h_parents
ffff80008115a9c0 d mjc_parents
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ffff80008115ab40 d i2s3_m_ck_parents
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ffff80008115ac08 d camtg_parents
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ffff80008115ac80 d axi_mfg_in_parents
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ffff80008115acb8 d aud_intbus_parents
ffff80008115acf0 d aud_2_parents
ffff80008115ad10 d aud_1_parents
ffff80008115ad30 d of_match_clk_mt6795_mfg
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ffff80008115b058 d clk_mt6795_mm_id_table
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ffff80008115bbc0 d of_match_clk_mt6795_vdecsys
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ffff80008115be68 d vdec0_cg_regs
ffff80008115be78 d of_match_clk_mt6795_vencsys
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ffff80008115c1a0 d plls
ffff80008115c740 d infra_fixed_divs
ffff80008115c768 d top_fixed_divs
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ffff80008115d818 d of_match_clk_mt6797
ffff80008115db38 d infra_clks
ffff80008115eff8 d infra2_cg_regs
ffff80008115f008 d infra1_cg_regs
ffff80008115f018 d infra0_cg_regs
ffff80008115f028 d anc_md32_parents
ffff80008115f040 d mfg_52m_parents
ffff80008115f060 d audio_h_parents
ffff80008115f080 d bsi_spi_parents
ffff80008115f0a0 d spm_parents
ffff80008115f0b0 d ssusb_top_sys_parents
ffff80008115f0c0 d aud_2_parents
ffff80008115f0d0 d aud_1_parents
ffff80008115f0e0 d dpi0_parents
ffff80008115f118 d mjc_parents
ffff80008115f138 d atb_parents
ffff80008115f150 d scp_parents
ffff80008115f170 d pmicspi_parents
ffff80008115f1a8 d aud_intbus_parents
ffff80008115f1c0 d audio_parents
ffff80008115f1e0 d msdc30_2_parents
ffff80008115f218 d msdc30_1_parents
ffff80008115f250 d msdc50_0_parents
ffff80008115f298 d msdc50_0_hclk_parents
ffff80008115f2b8 d usb20_parents
ffff80008115f2d0 d ulposc_spi_ck_mux_parents
ffff80008115f2e0 d spi_parents
ffff80008115f300 d uart_parents
ffff80008115f310 d camtg
ffff80008115f328 d mfg_parents
ffff80008115f348 d venc_parents
ffff80008115f360 d vdec_parents
ffff80008115f398 d pwm_parents
ffff80008115f3d0 d mm_parents
ffff80008115f3f0 d ddrphycfg_parents
ffff80008115f410 d ulposc_axi_ck_mux_pre_parents
ffff80008115f420 d ulposc_axi_ck_mux_parents
ffff80008115f430 d axi_parents
ffff80008115f448 d plls
ffff80008115f8c8 d __func__.15
ffff80008115f8e8 d of_match_clk_mt7981_apmixed
ffff80008115fa78 d of_match_clk_mt7981_topckgen
ffff80008115fc08 d topck_desc
ffff80008115fc90 d top_muxes
ffff8000811608f0 d top_divs
ffff8000811614d0 d of_match_clk_mt7981_infracfg
ffff800081161660 d infracfg_desc
ffff8000811616e8 d infra_clks
ffff800081162328 d infra2_cg_regs
ffff800081162338 d infra1_cg_regs
ffff800081162348 d infra0_cg_regs
ffff800081162358 d infra_muxes
ffff800081162778 d infra_divs
ffff8000811627a0 d of_match_clk_mt7981_eth
ffff800081162ac0 d sgmii1_desc
ffff800081162b48 d sgmii0_desc
ffff800081162bd0 d eth_desc
ffff800081162c58 d eth_clks
ffff800081162d58 d eth_cg_regs
ffff800081162d68 d sgmii1_clks
ffff800081162e68 d sgmii1_cg_regs
ffff800081162e78 d sgmii0_clks
ffff800081162f78 d sgmii0_cg_regs
ffff800081162f88 d plls
ffff800081163408 d __func__.15
ffff800081163428 d of_match_clk_mt7986_apmixed
ffff8000811635b8 d of_match_clk_mt7986_topckgen
ffff800081163748 d topck_desc
ffff8000811637d0 d top_muxes
ffff8000811645b0 d top_divs
ffff800081164998 d top_fixed_clks
ffff8000811649d8 d of_match_clk_mt7986_infracfg
ffff800081164b68 d infra_desc
ffff800081164bf0 d infra_clks
ffff800081165770 d infra2_cg_regs
ffff800081165780 d infra1_cg_regs
ffff800081165790 d infra0_cg_regs
ffff8000811657a0 d infra_muxes
ffff800081165b00 d infra_divs
ffff800081165b28 d of_match_clk_mt7986_eth
ffff800081165e48 d sgmii1_desc
ffff800081165ed0 d sgmii0_desc
ffff800081165f58 d eth_desc
ffff800081165fe0 d eth_clks
ffff800081166120 d eth_cg_regs
ffff800081166130 d sgmii1_clks
ffff800081166230 d sgmii1_cg_regs
ffff800081166240 d sgmii0_clks
ffff800081166340 d sgmii0_cg_regs
ffff800081166350 d plls
ffff800081166a10 d of_match_clk_mt7988_apmixed
ffff800081166ba0 d of_match_clk_mt7988_topckgen
ffff800081166df8 d mcusys_desc
ffff800081166e80 d mcu_arm_div_parents
ffff800081166e98 d mcu_bus_div_parents
ffff800081166eb0 d topck_desc
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ffff800081166f70 d top_muxes
ffff800081168b30 d eth_mii_parents
ffff800081168b40 d netsys_tops_400m_parents
ffff800081168b50 d macsec_parents
ffff800081168b68 d mcusys_backup_625m_parents
ffff800081168b78 d da_xtp_glb_p0_parents
ffff800081168b88 d dramc_md32_parents
ffff800081168ba0 d npu_tops_parents
ffff800081168bb0 d bus_tops_parents
ffff800081168bc8 d eth_xgmii_parents
ffff800081168be0 d eth_sys_200m_parents
ffff800081168bf0 d eth_refck_50m_parents
ffff800081168c00 d sysapb_parents
ffff800081168c10 d sgm_0_parents
ffff800081168c20 d usxgmii_sbus_0_parents
ffff800081168c30 d sspxtp_parents
ffff800081168c40 d aud_l_parents
ffff800081168c58 d a1sys_parents
ffff800081168c68 d aud_parents
ffff800081168c78 d usb_frmcnt_parents
ffff800081168c88 d pextp_tl_ck_parents
ffff800081168cb0 d pcie_mbist_250m_parents
ffff800081168cc0 d i2c_parents
ffff800081168ce0 d pwm_parents
ffff800081168d10 d spinfi_parents
ffff800081168d50 d nfi1x_parents
ffff800081168d90 d spi_parents
ffff800081168dd0 d emmc_400m_parents
ffff800081168e00 d emmc_250m_parents
ffff800081168e18 d uart_parents
ffff800081168e30 d axi_infra_parents
ffff800081168e40 d eip197_parents
ffff800081168e70 d netsys_mcu_parents
ffff800081168ea0 d eth_gmii_parents
ffff800081168eb0 d netsys_gsw_parents
ffff800081168ec8 d netsys_2x_parents
ffff800081168ee0 d netsys_500m_parents
ffff800081168ef8 d netsys_parents
ffff800081168f10 d top_divs
ffff800081169398 d top_fixed_clks
ffff8000811693b8 d of_match_clk_mt7988_infracfg
ffff800081169548 d infra_desc
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ffff80008116a9d0 d infra3_cg_regs
ffff80008116a9e0 d infra2_cg_regs
ffff80008116a9f0 d infra1_cg_regs
ffff80008116aa00 d infra0_cg_regs
ffff80008116aa10 d infra_muxes
ffff80008116b130 d of_match_clk_mt7988_eth
ffff80008116b518 d ethwarp_desc
ffff80008116b5a0 d ethwarp_rst_desc
ffff80008116b5c8 d ethwarp_clks
ffff80008116b688 d ethwarp_cg_regs
ffff80008116b698 d sgmii1_desc
ffff80008116b720 d sgmii1_clks
ffff80008116b7a0 d sgmii0_desc
ffff80008116b828 d sgmii0_clks
ffff80008116b8a8 d sgmii_cg_regs
ffff80008116b8b8 d ethdma_desc
ffff80008116b940 d ethdma_clks
ffff80008116bb80 d ethdma_cg_regs
ffff80008116bb90 d of_match_clk_mt7988_xfipll
ffff80008116bd20 d xfipll_desc
ffff80008116bda8 d xfipll_clks
ffff80008116bde8 d xfipll_divs
ffff80008116be10 d xfipll_cg_regs
ffff80008116be20 d plls
ffff80008116c2a0 d adj_divs
ffff80008116c2d0 d of_match_clk_mt8167_apmixed
ffff80008116c460 d mmpll_div_table
ffff80008116c4c0 d of_match_clk_mt8167
ffff80008116c718 d infra_desc
ffff80008116c7a0 d topck_desc
ffff80008116c828 d top_clks
ffff80008116e1a8 d top5_cg_regs
ffff80008116e1b8 d top4_cg_regs
ffff80008116e1c8 d top3_cg_regs
ffff80008116e1d8 d top2_cg_regs
ffff80008116e1e8 d top1_cg_regs
ffff80008116e1f8 d top0_cg_regs
ffff80008116e208 d top_adj_divs
ffff80008116e3b8 d ifr_muxes
ffff80008116e4d0 d ifr_i2c0_parents
ffff80008116e4e0 d ifr_eth_25m_parents
ffff80008116e4f0 d ifr_mux1_parents
ffff80008116e510 d nfiecc_parents
ffff80008116e538 d csw_nfiecc_parents
ffff80008116e560 d dbg_atclk_parents
ffff80008116e588 d bsi_parents
ffff80008116e5a8 d uart2_parents
ffff80008116e5b8 d aud_spdifin_parents
ffff80008116e5c8 d spi_parents
ffff80008116e5e8 d pwm_parents
ffff80008116e5f8 d aud_i2s0_m_parents
ffff80008116e608 d i2c_parents
ffff80008116e628 d aud_engen2_parents
ffff80008116e648 d aud_engen1_parents
ffff80008116e668 d aud2_parents
ffff80008116e678 d aud1_parents
ffff80008116e688 d slow_mfg_parents
ffff80008116e6a0 d axi_mfg_in_parents
ffff80008116e6c0 d dpi1_mm_parents
ffff80008116e6e8 d dpi0_mm_parents
ffff80008116e710 d vdec_mm_parents
ffff80008116e740 d eth_parents
ffff80008116e768 d msdc2_parents
ffff80008116e7a8 d spinor_parents
ffff80008116e7e8 d scam_mm_parents
ffff80008116e810 d usb_78m_parents
ffff80008116e838 d smi_mm_parents
ffff80008116e8a0 d ddrphycfg_parents
ffff80008116e8b0 d mfg_mm_parents
ffff80008116e9d8 d nfi1x_pad_parents
ffff80008116e9e8 d nfi2x_pad_parents
ffff80008116ec90 d aud_intbus_parents
ffff80008116ecb8 d qaxi_aud26m_parents
ffff80008116ecc8 d pmicspi_parents
ffff80008116ece8 d spm_52m_parents
ffff80008116ecf8 d msdc1_parents
ffff80008116ed38 d uart1_parents
ffff80008116ed48 d pwm_mm_parents
ffff80008116ed58 d camtg_mm_parents
ffff80008116ed80 d msdc0_parents
ffff80008116edc0 d csw_mux_mfg_parents
ffff80008116ee00 d ahb_infra_parents
ffff80008116ee68 d emi_ddrphy_parents
ffff80008116ee78 d gfmux_emi1x_parents
ffff80008116ee88 d uart0_parents
ffff80008116ee98 d top_divs
ffff80008116f6e0 d fixed_clks
ffff80008116f7a0 d of_match_clk_mt8167_audsys
ffff80008116f930 d aud_desc
ffff80008116f9b8 d aud_clks
ffff80008116fcf8 d aud_cg_regs
ffff80008116fd08 d of_match_clk_mt8167_imgsys
ffff80008116fe98 d img_desc
ffff80008116ff20 d img_clks
ffff8000811700a0 d img_cg_regs
ffff8000811700b0 d of_match_clk_mt8167_mfgcfg
ffff800081170240 d mfg_desc
ffff8000811702c8 d mfg_clks
ffff8000811703c8 d mfg_cg_regs
ffff8000811703d8 d clk_mt8167_mm_id_table
ffff800081170418 d mm_desc
ffff8000811704a0 d mm_clks
ffff800081170d20 d mm1_cg_regs
ffff800081170d30 d mm0_cg_regs
ffff800081170d40 d of_match_clk_mt8167_vdec
ffff800081170ed0 d vdec_desc
ffff800081170f58 d vdec_clks
ffff800081170fd8 d vdec1_cg_regs
ffff800081170fe8 d vdec0_cg_regs
ffff800081170ff8 d plls
ffff800081171628 d apmixed_clks
ffff8000811718e8 d of_match_clk_mt8183_apmixed
ffff800081171a78 d mfgpll_div_table
ffff800081171ad8 d armpll_div_table
ffff800081171b38 d apmixed_cg_regs
ffff800081171b50 d top_muxes
ffff800081172b10 d of_match_clk_mt8183
ffff800081172ef8 d topck_desc
ffff800081172f80 d peri_desc
ffff800081173008 d mcu_desc
ffff800081173090 d infra_desc
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ffff800081173140 d peri_clks
ffff800081173180 d peri_cg_regs
ffff800081173190 d infra_clks
ffff800081174ad0 d infra3_cg_regs
ffff800081174ae0 d infra2_cg_regs
ffff800081174af0 d infra1_cg_regs
ffff800081174b00 d infra0_cg_regs
ffff800081174b10 d top_clks
ffff800081174b90 d top_cg_regs
ffff800081174ba0 d mcu_bus_parents
ffff800081174bc0 d mcu_mp2_parents
ffff800081174be0 d mcu_mp0_parents
ffff800081174c00 d apll_i2s5_parents
ffff800081174c10 d apll_i2s4_parents
ffff800081174c20 d apll_i2s3_parents
ffff800081174c30 d apll_i2s2_parents
ffff800081174c40 d apll_i2s1_parents
ffff800081174c50 d apll_i2s0_parents
ffff800081174c60 d aud_2_parents
ffff800081174c70 d aud_1_parents
ffff800081174c80 d fufs_parents
ffff800081174ca0 d faes_ufsfde_parents
ffff800081174cd0 d aud_engen2_parents
ffff800081174cf0 d aud_engen1_parents
ffff800081174d10 d dxcc_parents
ffff800081174d30 d seninf_parents
ffff800081174d50 d scp_parents
ffff800081174d88 d i2c_parents
ffff800081174da0 d spm_parents
ffff800081174db0 d ssusb_top_xhci_parents
ffff800081174dd0 d usb_top_parents
ffff800081174df0 d disppwm_parents
ffff800081174e18 d scam_parents
ffff800081174e28 d dpi0_parents
ffff800081174e70 d sspm_parents
ffff800081174e98 d atb_parents
ffff800081174eb0 d fpwrap_ulposc_parents
ffff800081174ed0 d pmicspi_parents
ffff800081174ee8 d aud_intbus_parents
ffff800081174f00 d audio_parents
ffff800081174f20 d msdc30_2_parents
ffff800081174f48 d msdc30_1_parents
ffff800081174f70 d msdc50_0_parents
ffff800081174fa0 d msdc50_hclk_parents
ffff800081174fb8 d spi_parents
ffff800081174fd8 d uart_parents
ffff800081174fe8 d camtg4_parents
ffff800081175028 d camtg3_parents
ffff800081175068 d camtg2_parents
ffff8000811750a8 d camtg_parents
ffff8000811750e8 d f52m_mfg_parents
ffff800081175108 d mfg_parents
ffff800081175128 d ipu_if_parents
ffff800081175170 d dsp2_parents
ffff8000811751b8 d dsp1_parents
ffff800081175200 d dsp_parents
ffff800081175248 d cam_parents
ffff800081175298 d img_parents
ffff8000811752d8 d mm_parents
ffff800081175308 d axi_parents
ffff800081175328 d top_divs
ffff800081175e90 d top_fixed_clks
ffff800081175ef0 d plls
ffff8000811766d0 d of_match_clk_mt8186_apmixed
ffff800081176860 d of_match_clk_mt8186_topck
ffff8000811769f0 d topck_desc
ffff800081176a80 d top_mtk_muxes
ffff800081178220 d apll_mck_parents
ffff800081178230 d adsp_bus_parents
ffff800081178268 d u3_occ_500m_parents
ffff800081178278 d u3_occ_250m_parents
ffff800081178288 d dpi_parents
ffff8000811782c0 d wpe_parents
ffff800081178308 d ssusb_parents
ffff800081178320 d nna2_parents
ffff8000811783a0 d nna_parents
ffff800081178420 d spinor_parents
ffff800081178450 d spmi_mst_parents
ffff800081178488 d dsi_occ_parents
ffff8000811784a8 d dvfsrc_parents
ffff8000811784b8 d audiodsp_parents
ffff8000811784e8 d aes_fde_parents
ffff800081178508 d ufs_parents
ffff800081178528 d audio_h_parents
ffff800081178548 d mdp_parents
ffff800081178590 d disp_parents
ffff8000811785d8 d vdec_parents
ffff800081178610 d dpmaif_parents
ffff800081178638 d isp_parents
ffff800081178680 d venc_parents
ffff8000811786c0 d camtm_parents
ffff8000811786d8 d pwrap_ulposc_parents
ffff800081178710 d aes_msdcfde_parents
ffff800081178740 d seninf_parents
ffff800081178760 d pwm_parents
ffff800081178780 d i2c_parents
ffff8000811787a0 d spm_parents
ffff8000811787c0 d srck_parents
ffff8000811787d8 d usb_parents
ffff8000811787f0 d dxcc_parents
ffff800081178808 d sspm_parents
ffff800081178830 d disp_pwm_parents
ffff800081178858 d aud_engen2_parents
ffff800081178878 d aud_engen1_parents
ffff800081178898 d aud_2_parents
ffff8000811788a8 d aud_1_parents
ffff8000811788b8 d aud_intbus_parents
ffff8000811788d0 d audio_parents
ffff8000811788f0 d msdc30_1_parents
ffff800081178918 d msdc50_0_parents
ffff800081178950 d msdc5hclk_parents
ffff800081178970 d spi_parents
ffff8000811789b0 d uart_parents
ffff8000811789c0 d camtg_parents
ffff8000811789f8 d mfg_parents
ffff800081178a18 d scp_parents
ffff800081178a48 d axi_parents
ffff800081178a68 d top_divs
ffff8000811793c8 d top_fixed_clks
ffff800081179428 d of_match_clk_mt8186_infra_ao
ffff8000811795b8 d infra_ao_desc
ffff800081179640 d infra_ao_clks
ffff80008117af80 d infra_ao3_cg_regs
ffff80008117af90 d infra_ao2_cg_regs
ffff80008117afa0 d infra_ao1_cg_regs
ffff80008117afb0 d infra_ao0_cg_regs
ffff80008117afc0 d of_match_clk_mt8186_cam
ffff80008117b2e0 d cam_rawb_desc
ffff80008117b368 d cam_rawa_desc
ffff80008117b3f0 d cam_desc
ffff80008117b478 d cam_rawb_clks
ffff80008117b538 d cam_rawa_clks
ffff80008117b5f8 d cam_clks
ffff80008117b9b8 d cam_cg_regs
ffff80008117b9c8 d of_match_clk_mt8186_img
ffff80008117bc20 d img2_desc
ffff80008117bca8 d img1_desc
ffff80008117bd30 d img2_clks
ffff80008117beb0 d img1_clks
ffff80008117bfb0 d img_cg_regs
ffff80008117bfc0 d of_match_clk_mt8186_imp_iic_wrap
ffff80008117c150 d imp_iic_wrap_desc
ffff80008117c1d8 d imp_iic_wrap_clks
ffff80008117c458 d imp_iic_wrap_cg_regs
ffff80008117c468 d of_match_clk_mt8186_ipe
ffff80008117c5f8 d ipe_desc
ffff80008117c680 d ipe_clks
ffff80008117c880 d ipe_cg_regs
ffff80008117c890 d of_match_clk_mt8186_mcu
ffff80008117ca20 d mcu_desc
ffff80008117caa8 d mcu_armpll_bus_parents
ffff80008117cac8 d mcu_armpll_bl_parents
ffff80008117cae8 d mcu_armpll_ll_parents
ffff80008117cb08 d of_match_clk_mt8186_mdp
ffff80008117cc98 d mdp_desc
ffff80008117cd20 d mdp_clks
ffff80008117d2a0 d mdp2_cg_regs
ffff80008117d2b0 d mdp0_cg_regs
ffff80008117d2c0 d of_match_clk_mt8186_mfg
ffff80008117d450 d mfg_desc
ffff80008117d4d8 d mfg_clks
ffff80008117d518 d mfg_cg_regs
ffff80008117d528 d clk_mt8186_mm_id_table
ffff80008117d568 d mm_desc
ffff80008117d5f0 d mm_clks
ffff80008117dc30 d mm1_cg_regs
ffff80008117dc40 d mm0_cg_regs
ffff80008117dc50 d of_match_clk_mt8186_vdec
ffff80008117dde0 d vdec_desc
ffff80008117de68 d vdec_clks
ffff80008117e068 d vdec3_cg_regs
ffff80008117e078 d vdec2_cg_regs
ffff80008117e088 d vdec1_cg_regs
ffff80008117e098 d vdec0_cg_regs
ffff80008117e0a8 d of_match_clk_mt8186_venc
ffff80008117e238 d venc_desc
ffff80008117e2c0 d venc_clks
ffff80008117e3c0 d venc_cg_regs
ffff80008117e3d0 d of_match_clk_mt8186_wpe
ffff80008117e560 d wpe_desc
ffff80008117e5e8 d wpe_clks
ffff80008117e6e8 d wpe_cg_regs
ffff80008117e6f8 d apmixed_clks
ffff80008117e738 d plls
ffff80008117efa8 d of_match_clk_mt8188_apmixed
ffff80008117f138 d apmixed_cg_regs
ffff80008117f148 d top_clks
ffff80008117f648 d top_adj_divs
ffff80008117f798 d top_divs
ffff8000811803c8 d top_fixed_clks
ffff800081180488 d mfg_fast_ref_parents
ffff800081180498 d of_match_clk_mt8188_topck
ffff800081180628 d top1_cg_regs
ffff800081180638 d top0_cg_regs
ffff800081180648 d top_mtk_muxes
ffff800081182868 d srck_parents
ffff800081182878 d ulposc_parents
ffff800081182898 d spinor_parents
ffff8000811828b8 d ecc_parents
ffff8000811828e8 d a4sys_parents
ffff800081182908 d a3sys_parents
ffff800081182928 d a2sys_parents
ffff800081182938 d a1sys_hp_parents
ffff800081182948 d aud_iec_parents
ffff800081182978 d dptx_parents
ffff8000811829a8 d i2si2_parents
ffff8000811829d8 d i2si1_parents
ffff800081182a08 d i2so2_parents
ffff800081182a38 d i2so1_parents
ffff800081182a68 d apll5_parents
ffff800081182a78 d apll4_parents
ffff800081182a88 d apll3_parents
ffff800081182a98 d apll2_parents
ffff800081182aa8 d apll1_parents
ffff800081182ab8 d asm_l_parents
ffff800081182ad8 d asm_h_parents
ffff800081182af8 d audio_local_bus_parents
ffff800081182b58 d adsp_parents
ffff800081182bb8 d snps_eth_50m_rmii_parents
ffff800081182bc8 d snps_eth_62p4m_ptp_parents
ffff800081182be8 d snps_eth_250m_parents
ffff800081182bf8 d hdmi_apb_parents
ffff800081182c10 d hdcp_24m_parents
ffff800081182c30 d hdcp_parents
ffff800081182c50 d wpe_vpp_parents
ffff800081182cc8 d dsi_occ_parents
ffff800081182ce8 d aes_msdcfde_parents
ffff800081182d18 d tl_parents
ffff800081182d30 d dvfsrc_parents
ffff800081182d50 d spmi_m_mst_parents
ffff800081182da0 d spmi_p_mst_parents
ffff800081182df0 d mcupm_parents
ffff800081182e08 d pwm_parents
ffff800081182e28 d vdec_parents
ffff800081182ea8 d venc_parents
ffff800081182f28 d gcpu_parents
ffff800081182f50 d seninf1_parents
ffff800081182f90 d seninf_parents
ffff800081182fd0 d i2c_parents
ffff800081182fe8 d ssusb_xhci_3p_parents
ffff800081183008 d usb_3p_parents
ffff800081183028 d ssusb_xhci_2p_parents
ffff800081183048 d usb_2p_parents
ffff800081183068 d ssusb_xhci_parents
ffff800081183088 d usb_parents
ffff8000811830a8 d disp_pwm1_parents
ffff8000811830d0 d disp_pwm0_parents
ffff800081183100 d dpi_parents
ffff800081183148 d edp_parents_idx
ffff800081183150 d edp_parents
ffff800081183178 d dp_parents_idx
ffff800081183180 d dp_parents
ffff8000811831a8 d sspm_parents
ffff8000811831d8 d atb_parents
ffff8000811831f0 d pwrap_ulposc_parents
ffff800081183230 d audio_h_parents
ffff800081183250 d aud_intbus_parents
ffff800081183268 d intdir_parents
ffff800081183288 d msdc30_2_parents
ffff8000811832b0 d msdc30_1_parents
ffff8000811832d8 d msdc50_0_parents
ffff800081183308 d msdc5hclk_parents
ffff800081183320 d spi_parents
ffff800081183360 d uart_parents
ffff800081183370 d camtg3_parents
ffff8000811833b0 d camtg2_parents
ffff8000811833f0 d camtg_parents
ffff800081183430 d mfg_core_tmp_parents
ffff800081183440 d dsp7_parents
ffff800081183480 d dsp6_parents
ffff8000811834c0 d dsp5_parents
ffff800081183500 d dsp4_parents
ffff800081183540 d dsp3_parents
ffff800081183580 d dsp2_parents
ffff8000811835c0 d dsp1_parents
ffff800081183600 d dsp_parents
ffff800081183640 d camtm_parents
ffff800081183660 d img_parents
ffff8000811836c8 d ccu_ahb_parents
ffff800081183718 d ccu_parents
ffff800081183768 d cam_parents
ffff8000811837c0 d ipe_parents
ffff800081183820 d ethdr_parents
ffff800081183898 d vpp_parents
ffff800081183910 d bus_aximem_parents
ffff800081183938 d scp_parents
ffff800081183978 d spm_parents
ffff800081183998 d axi_parents
ffff8000811839d0 d of_match_clk_mt8188_peri_ao
ffff800081183b60 d peri_ao_desc
ffff800081183be8 d peri_ao_clks
ffff800081183f28 d peri_ao_cg_regs
ffff800081183f38 d of_match_clk_mt8188_infra_ao
ffff8000811840c8 d infra_ao_desc
ffff800081184150 d infra_ao_rst_desc
ffff800081184178 d infra_ao_clks
ffff8000811854f8 d infra_ao4_cg_regs
ffff800081185508 d infra_ao3_cg_regs
ffff800081185518 d infra_ao2_cg_regs
ffff800081185528 d infra_ao1_cg_regs
ffff800081185538 d infra_ao0_cg_regs
ffff800081185548 d of_match_clk_mt8188_adsp_audio26m
ffff8000811856d8 d adsp_audio26m_desc
ffff800081185760 d adsp_audio26m_clks
ffff8000811857a0 d adsp_audio26m_cg_regs
ffff8000811857b0 d of_match_clk_mt8188_cam
ffff800081185c60 d cam_yuvb_desc
ffff800081185ce8 d cam_yuva_desc
ffff800081185d70 d cam_rawb_desc
ffff800081185df8 d cam_rawa_desc
ffff800081185e80 d cam_main_desc
ffff800081185f08 d cam_sys_rst_desc
ffff800081185f30 d cam_yuvb_clks
ffff800081185ff0 d cam_yuva_clks
ffff8000811860b0 d cam_rawb_clks
ffff800081186170 d cam_rawa_clks
ffff800081186230 d cam_main_clks
ffff800081186870 d cam_cg_regs
ffff800081186880 d of_match_clk_mt8188_ccu
ffff800081186a10 d ccu_desc
ffff800081186a98 d ccu_clks
ffff800081186b58 d ccu_cg_regs
ffff800081186b68 d of_match_clk_mt8188_imgsys_main
ffff8000811870e0 d imgsys1_dip_nr_desc
ffff800081187168 d imgsys1_dip_top_desc
ffff8000811871f0 d imgsys_wpe3_desc
ffff800081187278 d imgsys_wpe2_desc
ffff800081187300 d imgsys_wpe1_desc
ffff800081187388 d imgsys_main_desc
ffff800081187410 d img_sys_rst_desc
ffff800081187438 d imgsys1_dip_nr_clks
ffff8000811874b8 d imgsys1_dip_top_clks
ffff800081187538 d imgsys_wpe3_clks
ffff8000811875b8 d imgsys_wpe2_clks
ffff800081187638 d imgsys_wpe1_clks
ffff8000811876b8 d imgsys_main_clks
ffff800081187938 d imgsys_cg_regs
ffff800081187948 d of_match_clk_mt8188_imp_iic_wrap
ffff800081187c68 d imp_iic_wrap_en_desc
ffff800081187cf0 d imp_iic_wrap_w_desc
ffff800081187d78 d imp_iic_wrap_c_desc
ffff800081187e00 d imp_iic_wrap_en_clks
ffff800081187e80 d imp_iic_wrap_w_clks
ffff800081187f00 d imp_iic_wrap_c_clks
ffff800081187fc0 d imp_iic_wrap_cg_regs
ffff800081187fd0 d of_match_clk_mt8188_ipe
ffff800081188160 d ipe_desc
ffff8000811881e8 d ipe_sys_rst_desc
ffff800081188210 d ipe_clks
ffff800081188350 d ipe_cg_regs
ffff800081188360 d of_match_clk_mt8188_mfgcfg
ffff8000811884f0 d mfgcfg_desc
ffff800081188578 d mfgcfg_clks
ffff8000811885b8 d mfgcfg_cg_regs
ffff8000811885c8 d of_match_clk_mt8188_vdec
ffff800081188820 d vdec2_desc
ffff8000811888a8 d vdec1_desc
ffff800081188930 d vdec2_clks
ffff800081188a70 d vdec1_clks
ffff800081188c30 d vdec2_cg_regs
ffff800081188c40 d vdec1_cg_regs
ffff800081188c50 d vdec0_cg_regs
ffff800081188c60 d clk_mt8188_vdo0_id_table
ffff800081188ca0 d vdo0_desc
ffff800081188d28 d vdo0_clks
ffff800081189568 d vdo0_2_cg_regs
ffff800081189578 d vdo0_1_cg_regs
ffff800081189588 d vdo0_0_cg_regs
ffff800081189598 d clk_mt8188_vdo1_id_table
ffff8000811895d8 d vdo1_desc
ffff800081189660 d vdo1_clks
ffff80008118a5e0 d vdo1_5_cg_regs
ffff80008118a5f0 d vdo1_4_cg_regs
ffff80008118a600 d vdo1_3_cg_regs
ffff80008118a610 d vdo1_2_cg_regs
ffff80008118a620 d vdo1_1_cg_regs
ffff80008118a630 d vdo1_0_cg_regs
ffff80008118a640 d of_match_clk_mt8188_venc1
ffff80008118a7d0 d venc1_desc
ffff80008118a858 d venc1_clks
ffff80008118aa18 d venc1_cg_regs
ffff80008118aa28 d clk_mt8188_vpp0_id_table
ffff80008118aa68 d vpp0_desc
ffff80008118aaf0 d vpp0_clks
ffff80008118b630 d vpp0_2_cg_regs
ffff80008118b640 d vpp0_1_cg_regs
ffff80008118b650 d vpp0_0_cg_regs
ffff80008118b660 d clk_mt8188_vpp1_id_table
ffff80008118b6a0 d vpp1_desc
ffff80008118b728 d vpp1_clks
ffff80008118c428 d vpp1_1_cg_regs
ffff80008118c438 d vpp1_0_cg_regs
ffff80008118c448 d of_match_clk_mt8188_wpe
ffff80008118c6a0 d wpe_vpp0_desc
ffff80008118c728 d wpe_top_desc
ffff80008118c7b0 d wpe_vpp0_clks
ffff80008118cd70 d wpe_top_clks
ffff80008118ce70 d wpe_vpp0_1_cg_regs
ffff80008118ce80 d wpe_vpp0_0_cg_regs
ffff80008118ce90 d wpe_top_cg_regs
ffff80008118cea0 d apmixed_clks
ffff80008118cee0 d plls
ffff80008118d480 d of_match_clk_mt8192_apmixed
ffff80008118d610 d apmixed_cg_regs
ffff80008118d620 d of_match_clk_mt8192
ffff80008118d940 d topck_desc
ffff80008118d9c8 d peri_desc
ffff80008118da50 d infra_desc
ffff80008118dad8 d clk_rst_desc
ffff80008118db00 d top_clks
ffff80008118db80 d top_cg_regs
ffff80008118db90 d peri_clks
ffff80008118dbd0 d peri_cg_regs
ffff80008118dbe0 d infra_clks
ffff80008118fa20 d infra5_cg_regs
ffff80008118fa30 d infra4_cg_regs
ffff80008118fa40 d infra3_cg_regs
ffff80008118fa50 d infra2_cg_regs
ffff80008118fa60 d infra1_cg_regs
ffff80008118fa70 d infra0_cg_regs
ffff80008118fa80 d top_mtk_muxes
ffff8000811910a0 d apll_i2s_m_parents
ffff8000811910b0 d sflash_parents
ffff8000811910d0 d aes_msdcfde_parents
ffff800081191100 d spmi_mst_parents
ffff800081191138 d audio_h_parents
ffff800081191158 d pwm_parents
ffff800081191168 d camtm_parents
ffff800081191188 d vdec_parents
ffff800081191208 d venc_parents
ffff800081191288 d dpmaif_main_parents
ffff8000811912b0 d adsp_parents
ffff8000811912f0 d aud_2_parents
ffff800081191300 d aud_1_parents
ffff800081191310 d ufs_parents
ffff800081191348 d aes_ufsfde_parents
ffff800081191380 d aud_engen2_parents
ffff8000811913a0 d aud_engen1_parents
ffff8000811913c0 d dxcc_parents
ffff8000811913e0 d tl_parents
ffff8000811913f8 d seninf_parents
ffff800081191438 d i2c_parents
ffff800081191450 d ssusb_xhci_parents
ffff800081191470 d usb_top_parents
ffff800081191490 d disp_pwm_parents
ffff8000811914b8 d scam_parents
ffff8000811914c8 d dpi_parents
ffff8000811914f0 d atb_parents
ffff800081191508 d pwrap_ulposc_parents
ffff800081191530 d aud_intbus_parents
ffff800081191548 d audio_parents
ffff800081191568 d msdc30_parents
ffff800081191590 d msdc50_0_parents
ffff8000811915c0 d msdc50_0_h_parents
ffff8000811915d8 d spi_parents
ffff8000811915f8 d uart_parents
ffff800081191608 d camtg_parents
ffff800081191648 d mfg_pll_parents
ffff800081191658 d mfg_ref_parents
ffff800081191678 d dsp7_parents
ffff8000811916b8 d ccu_parents
ffff800081191708 d cam_parents
ffff800081191758 d dpe_parents
ffff800081191798 d ipe_parents
ffff8000811917e0 d img_parents
ffff800081191840 d mdp_parents
ffff800081191898 d disp_parents
ffff8000811918e8 d bus_aximem_parents
ffff800081191910 d scp_parents
ffff800081191950 d spm_parents
ffff800081191970 d axi_parents
ffff8000811919a8 d top_divs
ffff8000811924e8 d top_fixed_clks
ffff800081192508 d of_match_clk_mt8192_aud
ffff800081192698 d aud_desc
ffff800081192720 d aud_clks
ffff800081192f20 d aud2_cg_regs
ffff800081192f30 d aud1_cg_regs
ffff800081192f40 d aud0_cg_regs
ffff800081192f50 d of_match_clk_mt8192_cam
ffff800081193338 d cam_rawc_desc
ffff8000811933c0 d cam_rawb_desc
ffff800081193448 d cam_rawa_desc
ffff8000811934d0 d cam_desc
ffff800081193558 d cam_rawc_clks
ffff800081193618 d cam_rawb_clks
ffff8000811936d8 d cam_rawa_clks
ffff800081193798 d cam_clks
ffff800081193b98 d cam_cg_regs
ffff800081193ba8 d of_match_clk_mt8192_img
ffff800081193e00 d img2_desc
ffff800081193e88 d img_desc
ffff800081193f10 d img2_clks
ffff800081194090 d img_clks
ffff800081194190 d img_cg_regs
ffff8000811941a0 d of_match_clk_mt8192_imp_iic_wrap
ffff800081194718 d imp_iic_wrap_ws_desc
ffff8000811947a0 d imp_iic_wrap_w_desc
ffff800081194828 d imp_iic_wrap_s_desc
ffff8000811948b0 d imp_iic_wrap_n_desc
ffff800081194938 d imp_iic_wrap_e_desc
ffff8000811949c0 d imp_iic_wrap_c_desc
ffff800081194a48 d imp_iic_wrap_ws_clks
ffff800081194b08 d imp_iic_wrap_w_clks
ffff800081194b48 d imp_iic_wrap_s_clks
ffff800081194c08 d imp_iic_wrap_n_clks
ffff800081194c88 d imp_iic_wrap_e_clks
ffff800081194cc8 d imp_iic_wrap_c_clks
ffff800081194dc8 d imp_iic_wrap_cg_regs
ffff800081194dd8 d of_match_clk_mt8192_ipe
ffff800081194f68 d ipe_desc
ffff800081194ff0 d ipe_clks
ffff8000811951f0 d ipe_cg_regs
ffff800081195200 d of_match_clk_mt8192_mdp
ffff800081195390 d mdp_desc
ffff800081195418 d mdp_clks
ffff800081195998 d mdp1_cg_regs
ffff8000811959a8 d mdp0_cg_regs
ffff8000811959b8 d of_match_clk_mt8192_mfg
ffff800081195b48 d mfg_desc
ffff800081195bd0 d mfg_clks
ffff800081195c10 d mfg_cg_regs
ffff800081195c20 d clk_mt8192_mm_id_table
ffff800081195c60 d mm_desc
ffff800081195ce8 d mm_clks
ffff8000811965e8 d mm2_cg_regs
ffff8000811965f8 d mm1_cg_regs
ffff800081196608 d mm0_cg_regs
ffff800081196618 d of_match_clk_mt8192_msdc
ffff8000811967a8 d msdc_top_desc
ffff800081196830 d msdc_top_clks
ffff800081196bf0 d msdc_top_cg_regs
ffff800081196c00 d of_match_clk_mt8192_scp_adsp
ffff800081196d90 d scp_adsp_desc
ffff800081196e18 d scp_adsp_clks
ffff800081196e58 d scp_adsp_cg_regs
ffff800081196e68 d of_match_clk_mt8192_vdec
ffff8000811970c0 d vdec_soc_desc
ffff800081197148 d vdec_desc
ffff8000811971d0 d vdec_soc_clks
ffff800081197310 d vdec_clks
ffff800081197450 d vdec2_cg_regs
ffff800081197460 d vdec1_cg_regs
ffff800081197470 d vdec0_cg_regs
ffff800081197480 d of_match_clk_mt8192_venc
ffff800081197610 d venc_desc
ffff800081197698 d venc_clks
ffff800081197798 d venc_cg_regs
ffff8000811977a8 d apmixed_clks
ffff8000811977e8 d plls
ffff8000811984d8 d of_match_clk_mt8195_apmixed
ffff800081198668 d apmixed_cg_regs
ffff800081198678 d top_clks
ffff800081198bb8 d top_adj_divs
ffff800081198d08 d top_divs
ffff800081199af0 d top_fixed_clks
ffff800081199c70 d mfg_fast_parents
ffff800081199c80 d of_match_clk_mt8195_topck
ffff800081199e10 d top1_cg_regs
ffff800081199e20 d top0_cg_regs
ffff800081199e30 d top_mtk_muxes
ffff80008119c9b0 d srck_parents
ffff80008119c9c0 d ulposc_core_parents
ffff80008119c9e0 d ulposc_parents
ffff80008119ca00 d dvio_dgi_ref_parents
ffff80008119ca38 d spinor_parents
ffff80008119ca58 d audio_local_bus_parents
ffff80008119cab8 d ecc_parents
ffff80008119cae8 d nfi1x_parents
ffff80008119cb28 d spinfi_b_parents
ffff80008119cb68 d a3sys_parents
ffff80008119cba0 d a2sys_parents
ffff80008119cbb0 d a1sys_hp_parents
ffff80008119cbc0 d i2s_parents
ffff80008119cbf8 d apll5_parents
ffff80008119cc08 d apll4_parents
ffff80008119cc18 d apll3_parents
ffff80008119cc28 d apll2_parents
ffff80008119cc38 d apll1_parents
ffff80008119cc48 d asm_parents
ffff80008119cc68 d adsp_parents
ffff80008119ccc8 d nna_parents
ffff80008119cd28 d dgi_out_parents
ffff80008119cd58 d snps_eth_50m_rmii_parents
ffff80008119cd68 d snps_eth_62p4m_ptp_parents
ffff80008119cd88 d snps_eth_250m_parents
ffff80008119cd98 d hdmi_apb_parents
ffff80008119cdb0 d hdmi_xtal_parents
ffff80008119cdc0 d hd20_hdcp_c_parents
ffff80008119cde0 d hd20_dacr_ref_parents
ffff80008119ce00 d hdcp_24m_parents
ffff80008119ce20 d hdcp_parents
ffff80008119ce40 d wpe_vpp_parents
ffff80008119ceb8 d dsi_occ_parents
ffff80008119ced8 d tl_parents
ffff80008119cef0 d dvfsrc_parents
ffff80008119cf10 d spmi_parents
ffff80008119cf60 d mcupm_parents
ffff80008119cf78 d pwm_parents
ffff80008119cf88 d vdec_parents
ffff80008119d008 d venc_parents
ffff80008119d088 d ufs_mp_sap_parents
ffff80008119d098 d ufs_tick1us_parents
ffff80008119d0a8 d ufs_parents
ffff80008119d0e0 d aes_fde_parents
ffff80008119d110 d dpmaif_parents
ffff80008119d138 d dxcc_parents
ffff80008119d158 d gcpu_parents
ffff80008119d180 d seninf_parents
ffff80008119d1c0 d i2c_parents
ffff80008119d1d8 d usb_parents
ffff80008119d1f8 d disp_pwm_parents
ffff80008119d220 d edp_parents_idx
ffff80008119d228 d edp_parents
ffff80008119d250 d dp_parents_idx
ffff80008119d258 d dp_parents
ffff80008119d280 d pwrmcu_parents
ffff80008119d2b0 d atb_parents
ffff80008119d2c8 d pwrap_ulposc_parents
ffff80008119d308 d audio_h_parents
ffff80008119d328 d aud_intbus_parents
ffff80008119d340 d intdir_parents
ffff80008119d360 d msdc30_parents
ffff80008119d388 d msdc50_0_parents
ffff80008119d3b8 d msdc50_0_h_parents
ffff80008119d3d0 d spis_parents
ffff80008119d410 d spi_parents
ffff80008119d450 d uart_parents
ffff80008119d460 d camtg_parents
ffff80008119d4a0 d mfg_parents
ffff80008119d4b0 d ipu_if_parents
ffff80008119d4f0 d dsp2_parents
ffff80008119d530 d dsp1_parents
ffff80008119d570 d dsp_parents
ffff80008119d5b0 d camtm_parents
ffff80008119d5d0 d img_parents
ffff80008119d630 d ccu_parents
ffff80008119d680 d cam_parents
ffff80008119d6d0 d ipe_parents
ffff80008119d728 d ethdr_parents
ffff80008119d7a0 d vpp_parents
ffff80008119d818 d bus_aximem_parents
ffff80008119d840 d scp_parents
ffff80008119d880 d spm_parents
ffff80008119d8a0 d axi_parents
ffff80008119d8d8 d of_match_clk_mt8195_peri_ao
ffff80008119da68 d peri_ao_desc
ffff80008119daf0 d peri_ao_clks
ffff80008119def0 d peri_ao_cg_regs
ffff80008119df00 d of_match_clk_mt8195_infra_ao
ffff80008119e090 d infra_ao_desc
ffff80008119e118 d infra_ao_clks
ffff80008119f898 d infra_ao4_cg_regs
ffff80008119f8a8 d infra_ao3_cg_regs
ffff80008119f8b8 d infra_ao2_cg_regs
ffff80008119f8c8 d infra_ao1_cg_regs
ffff80008119f8d8 d infra_ao0_cg_regs
ffff80008119f8e8 d apusys_plls
ffff80008119fb28 d of_match_clk_mt8195_apusys_pll
ffff80008119fcb8 d of_match_clk_mt8195_cam
ffff8000811a0230 d cam_yuvb_desc
ffff8000811a02b8 d cam_yuva_desc
ffff8000811a0340 d cam_rawb_desc
ffff8000811a03c8 d cam_rawa_desc
ffff8000811a0450 d cam_mraw_desc
ffff8000811a04d8 d cam_desc
ffff8000811a0560 d cam_yuvb_clks
ffff8000811a0620 d cam_yuva_clks
ffff8000811a06e0 d cam_rawb_clks
ffff8000811a07a0 d cam_rawa_clks
ffff8000811a0860 d cam_mraw_clks
ffff8000811a09e0 d cam_clks
ffff8000811a0fa0 d cam_cg_regs
ffff8000811a0fb0 d of_match_clk_mt8195_ccu
ffff8000811a1140 d ccu_desc
ffff8000811a11c8 d ccu_clks
ffff8000811a12c8 d ccu_cg_regs
ffff8000811a12d8 d of_match_clk_mt8195_img
ffff8000811a16c0 d img1_wpe_desc
ffff8000811a1748 d img1_dip_nr_desc
ffff8000811a17d0 d img1_dip_top_desc
ffff8000811a1858 d img_desc
ffff8000811a18e0 d img1_wpe_clks
ffff8000811a1960 d img1_dip_nr_clks
ffff8000811a19e0 d img1_dip_top_clks
ffff8000811a1a60 d img_clks
ffff8000811a1d20 d img_cg_regs
ffff8000811a1d30 d of_match_clk_mt8195_imp_iic_wrap
ffff8000811a1f88 d imp_iic_wrap_w_desc
ffff8000811a2010 d imp_iic_wrap_s_desc
ffff8000811a2098 d imp_iic_wrap_w_clks
ffff8000811a21d8 d imp_iic_wrap_s_clks
ffff8000811a2298 d imp_iic_wrap_cg_regs
ffff8000811a22a8 d of_match_clk_mt8195_ipe
ffff8000811a2438 d ipe_desc
ffff8000811a24c0 d ipe_clks
ffff8000811a2600 d ipe_cg_regs
ffff8000811a2610 d of_match_clk_mt8195_mfg
ffff8000811a27a0 d mfg_desc
ffff8000811a2828 d mfg_clks
ffff8000811a2868 d mfg_cg_regs
ffff8000811a2878 d of_match_clk_mt8195_scp_adsp
ffff8000811a2a08 d scp_adsp_desc
ffff8000811a2a90 d scp_adsp_clks
ffff8000811a2ad0 d scp_adsp_cg_regs
ffff8000811a2ae0 d of_match_clk_mt8195_vdec
ffff8000811a2e00 d vdec_soc_desc
ffff8000811a2e88 d vdec_core1_desc
ffff8000811a2f10 d vdec_desc
ffff8000811a2f98 d vdec_soc_clks
ffff8000811a3058 d vdec_core1_clks
ffff8000811a3118 d vdec_clks
ffff8000811a31d8 d vdec2_cg_regs
ffff8000811a31e8 d vdec1_cg_regs
ffff8000811a31f8 d vdec0_cg_regs
ffff8000811a3208 d clk_mt8195_vdo0_id_table
ffff8000811a3248 d vdo0_desc
ffff8000811a32d0 d vdo0_clks
ffff8000811a3e10 d vdo0_2_cg_regs
ffff8000811a3e20 d vdo0_1_cg_regs
ffff8000811a3e30 d vdo0_0_cg_regs
ffff8000811a3e40 d clk_mt8195_vdo1_id_table
ffff8000811a3e80 d vdo1_desc
ffff8000811a3f08 d vdo1_clks
ffff8000811a4bc8 d vdo1_4_cg_regs
ffff8000811a4bd8 d vdo1_3_cg_regs
ffff8000811a4be8 d vdo1_2_cg_regs
ffff8000811a4bf8 d vdo1_1_cg_regs
ffff8000811a4c08 d vdo1_0_cg_regs
ffff8000811a4c18 d of_match_clk_mt8195_venc
ffff8000811a4e70 d venc_core1_desc
ffff8000811a4ef8 d venc_desc
ffff8000811a4f80 d venc_core1_clks
ffff8000811a5100 d venc_clks
ffff8000811a5280 d venc_cg_regs
ffff8000811a5290 d clk_mt8195_vpp0_id_table
ffff8000811a52d0 d vpp0_desc
ffff8000811a5358 d vpp0_clks
ffff8000811a5dd8 d vpp0_2_cg_regs
ffff8000811a5de8 d vpp0_1_cg_regs
ffff8000811a5df8 d vpp0_0_cg_regs
ffff8000811a5e08 d clk_mt8195_vpp1_id_table
ffff8000811a5e48 d vpp1_desc
ffff8000811a5ed0 d vpp1_clks
ffff8000811a6b90 d vpp1_1_cg_regs
ffff8000811a6ba0 d vpp1_0_cg_regs
ffff8000811a6bb0 d of_match_clk_mt8195_wpe
ffff8000811a6ed0 d wpe_vpp1_desc
ffff8000811a6f58 d wpe_vpp0_desc
ffff8000811a6fe0 d wpe_desc
ffff8000811a7068 d wpe_vpp1_clks
ffff8000811a7628 d wpe_vpp0_clks
ffff8000811a7be8 d wpe_clks
ffff8000811a7da8 d wpe_vpp1_cg_regs
ffff8000811a7db8 d wpe_vpp0_cg_regs
ffff8000811a7dc8 d wpe_cg_regs
ffff8000811a7dd8 d of_match_clk_mt8196_apmixed
ffff8000811a8030 d apmixed2_desc
ffff8000811a8040 d apmixed2_plls
ffff8000811a8430 d apmixed_desc
ffff8000811a8440 d apmixed_plls
ffff8000811a88c0 d of_match_clk_mt8196_ck
ffff8000811a8a50 d topck_desc
ffff8000811a8ad8 d top_aud_divs
ffff8000811a8e58 d top_muxes
ffff8000811aa778 d sflash_parents
ffff8000811aa790 d apll_m_parents
ffff8000811aa7a0 d dxcc_parents
ffff8000811aa7c0 d spu_parents
ffff8000811aa7f0 d ssr_rng_parents
ffff8000811aa810 d ssr_kdf_parents
ffff8000811aa830 d ssr_parents
ffff8000811aa860 d smapparents
ffff8000811aa870 d dpsw_cmp_26m_parents
ffff8000811aa880 d uarthub_b_parents
ffff8000811aa898 d sdf_parents
ffff8000811aa8c8 d md_emi_parents
ffff8000811aa8d8 d tl_parents
ffff8000811aa8f8 d ipseast_parents
ffff8000811aa920 d mcupm_parents
ffff8000811aa948 d pwm_parents
ffff8000811aa960 d dpmaif_main_parents
ffff8000811aa9a8 d adsp_uarthub_b_parents
ffff8000811aa9c0 d adsp_parents
ffff8000811aa9d0 d aud_2_parents
ffff8000811aa9e0 d aud_1_parents
ffff8000811aa9f0 d ufs_parents
ffff8000811aaa28 d aes_ufsfde_parents
ffff8000811aaa58 d i2c_parents
ffff8000811aaa80 d usb_fmcnt_p1_parents
ffff8000811aaa90 d usb_1p_parents
ffff8000811aaaa0 d disp_pwm_parents
ffff8000811aaad8 d msdc30_parents
ffff8000811aab00 d spi_b_parents
ffff8000811aab40 d uart_parents
ffff8000811aab60 d mfg_eb_parents
ffff8000811aab80 d mfg_ref_parents
ffff8000811aab90 d dsp_parents
ffff8000811aabd0 d mcu_infra_parents
ffff8000811aac08 d mcu_l3gic_parents
ffff8000811aac28 d efuse_parents
ffff8000811aac38 d pbus_156m_parents
ffff8000811aac58 d cirq_parents
ffff8000811aac70 d atb_parents
ffff8000811aac90 d ap2conn_host_parents
ffff8000811aaca0 d emi_parents
ffff8000811aacd0 d p_noc_parents
ffff8000811aad30 d shared_sub_parents
ffff8000811aad88 d shared_axi_parents
ffff8000811aadc8 d io_noc_parents
ffff8000811aadf8 d mem_sub_parents
ffff8000811aae58 d axi_parents
ffff8000811aae88 d top_divs
ffff8000811ab5e0 d of_match_clk_mt8196_ck
ffff8000811ab770 d topck_desc
ffff8000811ab7f8 d top_muxes
ffff8000811ac158 d dvo_favt_parents
ffff8000811ac190 d dvo_parents
ffff8000811ac1b8 d mminfra_ao_parents
ffff8000811ac1d0 d mmup_parents
ffff8000811ac210 d mminfra_snoc_parents
ffff8000811ac288 d mminfra_parents
ffff8000811ac308 d mdp_parents
ffff8000811ac370 d disp_parents
ffff8000811ac3b8 d dp0_parents
ffff8000811ac3e0 d dp1_parents
ffff8000811ac408 d venc_parents
ffff8000811ac480 d ccutm_parents
ffff8000811ac4a8 d ccusys_parents
ffff8000811ac510 d vdec_parents
ffff8000811ac580 d dpe_parents
ffff8000811ac5d0 d camtm_parents
ffff8000811ac5f8 d cam_parents
ffff8000811ac678 d ipe_parents
ffff8000811ac6d0 d img1_parents
ffff8000811ac750 d seninf_parents
ffff8000811ac7d0 d top_divs
ffff8000811aced8 d vlp_plls
ffff8000811acff8 d vlp_muxes
ffff8000811adfb8 d vlp_divs
ffff8000811ae080 d vlpckgen_regmap_config
ffff8000811ae1b8 d of_match_clk_mt8196_vlp_ck
ffff8000811ae348 d vlp_spu1_vlp_parents
ffff8000811ae380 d vlp_spu0_vlp_parents
ffff8000811ae3b8 d vlp_spvlp_26m_parents
ffff8000811ae3c8 d vlp_aud_parent_index
ffff8000811ae3d0 d vlp_aud_intbus_parents
ffff8000811ae3e8 d vlp_aud_engen2_parents
ffff8000811ae400 d vlp_aud_engen1_parents
ffff8000811ae418 d vlp_audio_h_parents
ffff8000811ae430 d vlp_noc_vlp_parents
ffff8000811ae448 d vlp_usb_parents
ffff8000811ae458 d vlp_mminfra_parents
ffff8000811ae470 d vlp_spm_parents
ffff8000811ae480 d vlp_vlp_pbus_156m_parents
ffff8000811ae4a0 d vlp_dpmsrdma_parents
ffff8000811ae4b0 d vlp_debug_err_flag_parents
ffff8000811ae4c0 d vlp_vlp_pbus_26m_parents
ffff8000811ae4d0 d vlp_ulposc_sspm_parents
ffff8000811ae4e8 d vlp_sspm_26m_parents
ffff8000811ae4f8 d vlp_camtg2_7_parents
ffff8000811ae558 d vlp_camtg0_1_parents
ffff8000811ae5c0 d vlp_srck_parents
ffff8000811ae5d0 d vlp_sspm_parents
ffff8000811ae5f8 d vlp_systimer_26m_parents
ffff8000811ae608 d vlp_axi_vlp_parents
ffff8000811ae630 d vlp_pwm_vlp_parents
ffff8000811ae658 d vlp_dvfsrc_parents
ffff8000811ae668 d vlp_spmi_m_parents
ffff8000811ae688 d vlp_dpsw_central_parents
ffff8000811ae6a8 d vlp_dpsw_parents
ffff8000811ae6c8 d vlp_apxgpt_26m_b_parents
ffff8000811ae6d8 d vlp_spmi_32k_parents
ffff8000811ae700 d vlp_pwrap_ulposc_parents
ffff8000811ae720 d vlp_scp_iic_hs_parents
ffff8000811ae748 d vlp_scp_iic_parents
ffff8000811ae768 d vlp_scp_spi_parents
ffff8000811ae788 d vlp_scp_parents
ffff8000811ae7b8 d of_match_clk_mt8196_peri_ao
ffff8000811ae948 d peri_ao_mcd
ffff8000811ae9d0 d peri_ao_clks
ffff8000811af250 d peri_ao2_cg_regs
ffff8000811af260 d peri_ao1_hwv_regs
ffff8000811af270 d peri_ao1_cg_regs
ffff8000811af280 d peri_ao0_cg_regs
ffff8000811af290 d of_match_clk_mt8196_imp_iic_wrap
ffff8000811af678 d impw_mcd
ffff8000811af700 d impw_clks
ffff8000811af800 d impn_mcd
ffff8000811af888 d impn_clks
ffff8000811afa08 d impn_hwv_regs
ffff8000811afa18 d impe_mcd
ffff8000811afaa0 d impe_clks
ffff8000811afae0 d impc_mcd
ffff8000811afb68 d impc_clks
ffff8000811afc68 d imp_cg_regs
ffff8000811afc78 d of_match_clk_mt8196_mcu
ffff8000811b0128 d ptp_plls
ffff8000811b01b8 d cci_plls
ffff8000811b0248 d cpu_ll_plls
ffff8000811b02d8 d cpu_b_plls
ffff8000811b0368 d cpu_bl_plls
ffff8000811b03f8 d of_match_clk_mt8196_mdpsys
ffff8000811b0650 d mdp_mcd
ffff8000811b06d8 d mdp_clks
ffff8000811b1098 d mdp1_mcd
ffff8000811b1120 d mdp1_clks
ffff8000811b1ae0 d mdp2_cg_regs
ffff8000811b1af0 d mdp1_cg_regs
ffff8000811b1b00 d mdp0_cg_regs
ffff8000811b1b10 d of_match_clk_mt8196_pextp
ffff8000811b1d68 d pext1_mcd
ffff8000811b1df0 d pext1_rst_desc
ffff8000811b1e18 d pext1_clks
ffff8000811b2218 d pext_mcd
ffff8000811b22a0 d pext_rst_desc
ffff8000811b22c8 d pext_clks
ffff8000811b24c8 d pext_cg_regs
ffff8000811b24d8 d of_match_clk_mt8196_ufs_ao
ffff8000811b2668 d ufsao_mcd
ffff8000811b26f0 d ufsao_rst_desc
ffff8000811b2718 d ufsao_clks
ffff8000811b2918 d ufsao1_cg_regs
ffff8000811b2928 d ufsao0_cg_regs
ffff8000811b2938 d plls
ffff8000811b2f68 d of_match_clk_mt8365_apmixed
ffff8000811b30f8 d dsppll_div_table
ffff8000811b3158 d mfgpll_div_table
ffff8000811b31b8 d armpll_div_table
ffff8000811b3218 d of_match_clk_mt8365
ffff8000811b3600 d mcu_desc
ffff8000811b3688 d peri_desc
ffff8000811b3710 d infra_desc
ffff8000811b3798 d topck_desc
ffff8000811b3820 d peri_clks
ffff8000811b3860 d peri_cg_regs
ffff8000811b3870 d ifr_clks
ffff8000811b4a30 d ifr6_cg_regs
ffff8000811b4a40 d ifr5_cg_regs
ffff8000811b4a50 d ifr4_cg_regs
ffff8000811b4a60 d ifr3_cg_regs
ffff8000811b4a70 d ifr2_cg_regs
ffff8000811b4a80 d top_clk_gates
ffff8000811b4f40 d top2_cg_regs
ffff8000811b4f50 d top1_cg_regs
ffff8000811b4f60 d top0_cg_regs
ffff8000811b4f70 d top_adj_divs
ffff8000811b5120 d mcu_bus_parents
ffff8000811b5140 d top_muxes
ffff8000811b6160 d apll_i2s_parents
ffff8000811b6170 d mbist_diag_parents
ffff8000811b6188 d apu_parents
ffff8000811b61c8 d gcpu_cpm_parents
ffff8000811b61e0 d gcpu_parents
ffff8000811b6208 d eth_parents
ffff8000811b6230 d ecc_parents
ffff8000811b6258 d nfiecc_parents
ffff8000811b6298 d nfi2x_parents
ffff8000811b62d8 d dsp_parents
ffff8000811b6308 d dpi0_parents
ffff8000811b6330 d aes_fde_parents
ffff8000811b6360 d senif_parents
ffff8000811b6380 d pwm_parents
ffff8000811b6398 d i2c_parents
ffff8000811b63c0 d spm_parents
ffff8000811b63d0 d ssusb_sys_parents
ffff8000811b63f0 d dxcc_parents
ffff8000811b6410 d disp_pwm_parents
ffff8000811b6420 d aud_spdif_parents
ffff8000811b6430 d aud_engen2_parents
ffff8000811b6450 d aud_engen1_parents
ffff8000811b6470 d aud_2_parents
ffff8000811b6480 d aud_1_parents
ffff8000811b6490 d aud_intbus_parents
ffff8000811b64a8 d audio_parents
ffff8000811b64c8 d msdc30_1_parents
ffff8000811b6508 d msdc50_2_parents
ffff8000811b6548 d msdc50_0_parents
ffff8000811b6588 d msdc50_0_hc_parents
ffff8000811b65a8 d spi_parents
ffff8000811b65c8 d uart_parents
ffff8000811b65d8 d camtg_parents
ffff8000811b6610 d atb_parents
ffff8000811b6628 d mfg_parents
ffff8000811b6648 d scp_parents
ffff8000811b6680 d mm_parents
ffff8000811b66c0 d mem_parents
ffff8000811b66e0 d axi_parents
ffff8000811b6700 d top_divs
ffff8000811b6fc0 d top_fixed_clks
ffff8000811b7060 d of_match_clk_mt8365_apu
ffff8000811b71f0 d apu_desc
ffff8000811b7278 d apu_clks
ffff8000811b73f8 d apu_cg_regs
ffff8000811b7408 d of_match_clk_mt8365_cam
ffff8000811b7598 d cam_desc
ffff8000811b7620 d cam_clks
ffff8000811b7820 d cam_cg_regs
ffff8000811b7830 d of_match_clk_mt8365_mfg
ffff8000811b79c0 d mfg_desc
ffff8000811b7a48 d mfg_clks
ffff8000811b7ac8 d mfg1_cg_regs
ffff8000811b7ad8 d mfg0_cg_regs
ffff8000811b7ae8 d clk_mt8365_mm_id_table
ffff8000811b7b28 d mm_desc
ffff8000811b7bb0 d mm_clks
ffff8000811b84b0 d mm1_cg_regs
ffff8000811b84c0 d mm0_cg_regs
ffff8000811b84d0 d of_match_clk_mt8365_vdec
ffff8000811b8660 d vdec_desc
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ffff8000811c78d8 d artpec8_cmu_of_match
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ffff800081ea6ca5 d __setup_str_acpi_backlight
ffff800081ea6cb5 d __setup_str_acpi_irq_balance_set
ffff800081ea6cc6 d __setup_str_acpi_irq_nobalance_set
ffff800081ea6cd9 d __setup_str_acpi_irq_pci
ffff800081ea6ce7 d __setup_str_acpi_irq_isa
ffff800081ea6cf5 d __setup_str_acpi_gpe_set_masked_gpes
ffff800081ea6d04 d __setup_str_disable_acpi_watchdog
ffff800081ea6d18 d ac_dmi_table
ffff800081ea7120 d acpi_pci_slot_dmi_table
ffff800081ea73d0 d bat_dmi_table
ffff800081ea7a88 d __setup_str_setup_hest_disable
ffff800081ea7a95 d __setup_str_setup_erst_disable
ffff800081ea7aa2 d __setup_str_setup_bert_disable
ffff800081ea7ab0 d iort_arm_smmu_v3_pmcg_cfg
ffff800081ea7ae8 d iort_arm_smmu_cfg
ffff800081ea7b20 d iort_arm_smmu_v3_cfg
ffff800081ea7b58 d __setup_str_pnp_setup_reserve_mem
ffff800081ea7b69 d __setup_str_pnp_setup_reserve_io
ffff800081ea7b79 d __setup_str_pnp_setup_reserve_dma
ffff800081ea7b8a d __setup_str_pnp_setup_reserve_irq
ffff800081ea7b9b d __setup_str_pnpacpi_setup
ffff800081ea7ba4 d __setup_str_clk_ignore_unused_setup
ffff800081ea7bb8 d quirk_index
ffff800081ea7bc0 d wdt_mux_p
ffff800081ea7bd0 d usb_frmcnt_parents
ffff800081ea7be0 d u2u3_sys_parents
ffff800081ea7bf0 d u2u3_parents
ffff800081ea7c00 d a_tuner_parents
ffff800081ea7c18 d aud_l_parents
ffff800081ea7c30 d a1sys_parents
ffff800081ea7c40 d aud_parents
ffff800081ea7c50 d eip97b_parents
ffff800081ea7c78 d sgm_reg_parents
ffff800081ea7c88 d sgm_325m_parents
ffff800081ea7c98 d netsys_2x_parents
ffff800081ea7cb0 d netsys_mcu_parents
ffff800081ea7cd8 d netsys_500m_parents
ffff800081ea7ce8 d netsys_parents
ffff800081ea7cf8 d ap2cnn_host_parents
ffff800081ea7d08 d arm_db_main_parents
ffff800081ea7d18 d sysapb_parents
ffff800081ea7d28 d sysaxi_parents
ffff800081ea7d38 d dramc_md32_parents
ffff800081ea7d50 d csw_f26m_parents
ffff800081ea7d60 d emmc_400m_parents
ffff800081ea7d80 d emmc_208m_parents
ffff800081ea7db8 d pextp_tl_ck_parents
ffff800081ea7dd8 d i2c_parents
ffff800081ea7df8 d pwm_parents
ffff800081ea7e28 d uart_parents
ffff800081ea7e40 d spi_parents
ffff800081ea7e80 d spinfi_parents
ffff800081ea7ec0 d nfi1x_parents
ffff800081ea7f00 d infra_pcie_parents
ffff800081ea7f20 d infra_pwm_bsel_parents
ffff800081ea7f40 d infra_pwm1_parents
ffff800081ea7f48 d infra_spi1_parents
ffff800081ea7f58 d infra_spi0_parents
ffff800081ea7f68 d infra_uart_parent
ffff800081ea7f78 d da_u2_refsel_parents
ffff800081ea7f88 d u2u3_sys_parents
ffff800081ea7f98 d a_tuner_parents
ffff800081ea7fb0 d aud_l_parents
ffff800081ea7fc8 d eip_b_parents
ffff800081ea7fd8 d conn_mcusys_parents
ffff800081ea7fe8 d a1sys_parents
ffff800081ea7ff8 d sgm_reg_parents
ffff800081ea8008 d sgm_325m_parents
ffff800081ea8018 d netsys_2x_parents
ffff800081ea8038 d netsys_mcu_parents
ffff800081ea8060 d netsys_500m_parents
ffff800081ea8070 d netsys_parents
ffff800081ea8080 d arm_db_jtsel_parents
ffff800081ea8090 d arm_db_main_parents
ffff800081ea80a0 d sysapb_parents
ffff800081ea80b8 d sysaxi_parents
ffff800081ea80d0 d dramc_md32_parents
ffff800081ea80e0 d f_26m_adc_parents
ffff800081ea80f0 d emmc_416m_parents
ffff800081ea8100 d emmc_250m_parents
ffff800081ea8110 d pextp_tl_ck_parents
ffff800081ea8130 d i2c_parents
ffff800081ea8150 d pwm_parents
ffff800081ea8170 d uart_parents
ffff800081ea8188 d spi_parents
ffff800081ea81c8 d spinfi_parents
ffff800081ea8208 d nfi1x_parents
ffff800081ea8248 d infra_pcie_parents
ffff800081ea8268 d infra_pwm_bsel_parents
ffff800081ea8288 d infra_spi_parents
ffff800081ea8298 d infra_uart_parent
ffff800081ea82a8 d infra_pcie_gfmux_tl_ck_o_p3_parents
ffff800081ea82c8 d infra_pcie_gfmux_tl_ck_o_p2_parents
ffff800081ea82e8 d infra_pcie_gfmux_tl_ck_o_p1_parents
ffff800081ea8308 d infra_pcie_gfmux_tl_ck_o_p0_parents
ffff800081ea8328 d infra_pwm_bck_parents
ffff800081ea8348 d infra_mux_spi1_parents
ffff800081ea8358 d infra_mux_spi0_parents
ffff800081ea8368 d infra_mux_uart2_parents
ffff800081ea8378 d infra_mux_uart1_parents
ffff800081ea8388 d infra_mux_uart0_parents
ffff800081ea8398 d ifr_muxes
ffff800081ea84b0 d ifr_i2c0_parents
ffff800081ea84c0 d ifr_eth_25m_parents
ffff800081ea84d0 d ifr_mux1_parents
ffff800081ea84f0 d nfiecc_parents
ffff800081ea8518 d csw_nfiecc_parents
ffff800081ea8540 d dbg_atclk_parents
ffff800081ea8568 d bsi_parents
ffff800081ea8588 d uart2_parents
ffff800081ea8598 d aud_spdifin_parents
ffff800081ea85a8 d spi_parents
ffff800081ea85c8 d pwm_parents
ffff800081ea85d8 d aud_i2s0_m_parents
ffff800081ea85e8 d i2c_parents
ffff800081ea8608 d aud_engen2_parents
ffff800081ea8628 d aud_engen1_parents
ffff800081ea8648 d aud2_parents
ffff800081ea8658 d aud1_parents
ffff800081ea8668 d eth_parents
ffff800081ea8690 d msdc2_parents
ffff800081ea86d0 d spinor_parents
ffff800081ea8710 d usb_78m_parents
ffff800081ea8738 d nfi1x_pad_parents
ffff800081ea8748 d nfi2x_pad_parents
ffff800081ea89f0 d aud_intbus_parents
ffff800081ea8a18 d qaxi_aud26m_parents
ffff800081ea8a28 d pmicspi_parents
ffff800081ea8a48 d msdc1_parents
ffff800081ea8a88 d uart1_parents
ffff800081ea8a98 d msdc0_parents
ffff800081ea8ad8 d ahb_infra_parents
ffff800081ea8b40 d uart0_parents
ffff800081ea8b50 d top_divs
ffff800081ea9208 d fixed_clks
ffff800081ea9268 d mux_armclk_p
ffff800081ea9278 d px30_cru_critical_clocks
ffff800081ea9310 d mux_gpu_p
ffff800081ea9320 d mux_mipidsiphy_ref_p
ffff800081ea9330 d mux_usbphy_ref_p
ffff800081ea9340 d mux_uart0_pmu_p
ffff800081ea9358 d mux_wifi_pmu_p
ffff800081ea9368 d mux_rtc32k_pmu_p
ffff800081ea9380 d mux_gmac_rmii_sel_p
ffff800081ea9390 d mux_gmac_p
ffff800081ea93a0 d mux_sdmmc_p
ffff800081ea93b0 d mux_emmc_p
ffff800081ea93c0 d mux_sdio_p
ffff800081ea93d0 d mux_nandc_p
ffff800081ea93e0 d mux_dclk_vopl_p
ffff800081ea93f8 d mux_dclk_vopb_p
ffff800081ea9410 d mux_cif_out_p
ffff800081ea9430 d mux_uart5_p
ffff800081ea9448 d mux_uart4_p
ffff800081ea9460 d mux_uart3_p
ffff800081ea9478 d mux_uart2_p
ffff800081ea9490 d mux_uart1_p
ffff800081ea94a8 d mux_uart_src_p
ffff800081ea94c8 d mux_i2s0_rx_tx_p
ffff800081ea94d8 d mux_i2s0_tx_rx_p
ffff800081ea94e8 d mux_i2s2_out_p
ffff800081ea94f8 d mux_i2s1_out_p
ffff800081ea9508 d mux_i2s0_rx_out_p
ffff800081ea9520 d mux_i2s0_tx_out_p
ffff800081ea9538 d mux_i2s2_p
ffff800081ea9558 d mux_i2s1_p
ffff800081ea9578 d mux_i2s0_rx_p
ffff800081ea9598 d mux_i2s0_tx_p
ffff800081ea95b8 d mux_pdm_p
ffff800081ea95c8 d mux_gpll_xin24m_npll_p
ffff800081ea95e0 d mux_gpll_cpll_npll_xin24m_p
ffff800081ea9600 d mux_gpll_cpll_npll_p
ffff800081ea9618 d mux_gpll_xin24m_p
ffff800081ea9628 d mux_gpll_npll_p
ffff800081ea9638 d mux_gpll_cpll_p
ffff800081ea9648 d mux_npll_cpll_p
ffff800081ea9658 d mux_cpll_npll_p
ffff800081ea9668 d mux_4plls_p
ffff800081ea9688 d mux_ddrstdby_p
ffff800081ea9698 d mux_ddrphy_p
ffff800081ea96a8 d mux_usb480m_p
ffff800081ea96c0 d mux_pll_p
ffff800081ea96c8 d rk3308_critical_clocks
ffff800081ea9718 d mux_armclk_p
ffff800081ea9730 d mux_spdif_rx_p
ffff800081ea9740 d mux_spdif_rx_src_p
ffff800081ea9750 d mux_spdif_tx_p
ffff800081ea9768 d mux_spdif_tx_src_p
ffff800081ea9778 d mux_i2s1_2ch_out_p
ffff800081ea9788 d mux_i2s1_2ch_p
ffff800081ea97a0 d mux_i2s0_2ch_out_p
ffff800081ea97b0 d mux_i2s0_2ch_p
ffff800081ea97c8 d mux_i2s3_8ch_rx_tx_p
ffff800081ea97d8 d mux_i2s3_8ch_rx_p
ffff800081ea97f0 d mux_i2s3_8ch_tx_out_p
ffff800081ea9800 d mux_i2s3_8ch_tx_rx_p
ffff800081ea9810 d mux_i2s3_8ch_tx_p
ffff800081ea9828 d mux_i2s2_8ch_rx_tx_p
ffff800081ea9838 d mux_i2s2_8ch_rx_p
ffff800081ea9850 d mux_i2s2_8ch_tx_out_p
ffff800081ea9860 d mux_i2s2_8ch_tx_rx_p
ffff800081ea9870 d mux_i2s2_8ch_tx_p
ffff800081ea9888 d mux_i2s1_8ch_rx_tx_p
ffff800081ea9898 d mux_i2s1_8ch_rx_p
ffff800081ea98b0 d mux_i2s1_8ch_tx_out_p
ffff800081ea98c0 d mux_i2s1_8ch_tx_rx_p
ffff800081ea98d0 d mux_i2s1_8ch_tx_p
ffff800081ea98e8 d mux_i2s0_8ch_rx_tx_p
ffff800081ea98f8 d mux_i2s0_8ch_rx_p
ffff800081ea9910 d mux_i2s0_8ch_tx_out_p
ffff800081ea9920 d mux_i2s0_8ch_tx_rx_p
ffff800081ea9930 d mux_i2s0_8ch_tx_p
ffff800081ea9948 d mux_pdm_p
ffff800081ea9958 d mux_wifi_p
ffff800081ea9968 d mux_wifi_src_p
ffff800081ea9978 d mux_usbphy_ref_p
ffff800081ea9988 d mux_rtc32k_p
ffff800081ea99a8 d mux_ddrstdby_p
ffff800081ea99b8 d mux_mac_rmii_sel_p
ffff800081ea99c8 d mux_mac_p
ffff800081ea99d8 d mux_emmc_p
ffff800081ea99e8 d mux_sdio_p
ffff800081ea99f8 d mux_sdmmc_p
ffff800081ea9a08 d mux_nandc_p
ffff800081ea9a18 d mux_dclk_vop_p
ffff800081ea9a30 d mux_uart4_p
ffff800081ea9a48 d mux_uart3_p
ffff800081ea9a60 d mux_uart2_p
ffff800081ea9a78 d mux_uart1_p
ffff800081ea9a90 d mux_uart0_p
ffff800081ea9aa8 d mux_vpll0_vpll1_xin24m_p
ffff800081ea9ac0 d mux_vpll0_vpll1_p
ffff800081ea9ad0 d mux_dpll_vpll0_vpll1_usb480m_xin24m_p
ffff800081ea9af8 d mux_dpll_vpll0_vpll1_xin24m_p
ffff800081ea9b18 d mux_dpll_vpll0_vpll1_p
ffff800081ea9b30 d mux_dpll_vpll0_xin24m_p
ffff800081ea9b48 d mux_dpll_vpll0_p
ffff800081ea9b58 d mux_usb480m_p
ffff800081ea9b70 d mux_pll_p
ffff800081ea9b78 d rk3328_critical_clocks
ffff800081ea9cf8 d mux_armclk_p
ffff800081ea9d18 d mux_mac2io_ext_p
ffff800081ea9d28 d mux_mac2phy_src_p
ffff800081ea9d38 d mux_mac2io_src_p
ffff800081ea9d48 d mux_xin24m_32k_p
ffff800081ea9d58 d mux_ref_usb3otg_src_p
ffff800081ea9d68 d mux_aclk_peri_pre_p
ffff800081ea9d80 d mux_dclk_lcdc_p
ffff800081ea9d90 d mux_sclk_cif_p
ffff800081ea9da0 d mux_uart2_p
ffff800081ea9db8 d mux_uart1_p
ffff800081ea9dd0 d mux_uart0_p
ffff800081ea9de8 d mux_spdif_p
ffff800081ea9e08 d mux_i2s2out_p
ffff800081ea9e18 d mux_i2s1out_p
ffff800081ea9e28 d mux_i2s2_p
ffff800081ea9e48 d mux_i2s1_p
ffff800081ea9e68 d mux_i2s0_p
ffff800081ea9e88 d mux_usb480m_p
ffff800081ea9e98 d mux_hdmiphy_p
ffff800081ea9ea8 d mux_ddrphy_p
ffff800081ea9ec0 d mux_2plls_24m_u480m_p
ffff800081ea9ee0 d mux_2plls_u480m_p
ffff800081ea9ef8 d mux_4plls_p
ffff800081ea9f18 d mux_2plls_hdmiphy_p
ffff800081ea9f30 d mux_2plls_xin24m_p
ffff800081ea9f48 d mux_cpll_gpll_apll_p
ffff800081ea9f60 d mux_gpll_cpll_p
ffff800081ea9f70 d mux_2plls_p
ffff800081ea9f80 d mux_pll_p
ffff800081ea9f88 d rk3368_critical_clocks
ffff800081ea9fd8 d mux_armclkb_p
ffff800081ea9fe8 d mux_armclkl_p
ffff800081ea9ff8 d mux_mmc_src_p
ffff800081eaa018 d mux_mac_p
ffff800081eaa028 d mux_uart4_p
ffff800081eaa040 d mux_uart3_p
ffff800081eaa058 d mux_uart2_p
ffff800081eaa068 d mux_uart1_p
ffff800081eaa080 d mux_uart0_p
ffff800081eaa098 d mux_hsicphy480m_p
ffff800081eaa0b0 d mux_hsic_usbphy480m_p
ffff800081eaa0c0 d mux_usbphy480m_p
ffff800081eaa0d0 d mux_vip_out_p
ffff800081eaa0e0 d mux_edp_24m_p
ffff800081eaa0f0 d mux_spdif_8ch_p
ffff800081eaa110 d mux_i2s_2ch_p
ffff800081eaa130 d mux_i2s_8ch_clkout_p
ffff800081eaa140 d mux_i2s_8ch_pre_p
ffff800081eaa160 d mux_pll_src_cpll_gpll_npll_usb_p
ffff800081eaa180 d mux_pll_src_cpll_gpll_npll_npll_p
ffff800081eaa1a0 d mux_pll_src_cpll_gpll_usb_npll_p
ffff800081eaa1c0 d mux_pll_src_cpll_gpll_usb_usb_p
ffff800081eaa1e0 d mux_pll_src_cpll_gpll_usb_p
ffff800081eaa1f8 d mux_pll_src_npll_cpll_gpll_p
ffff800081eaa210 d mux_pll_src_cpll_gpll_npll_p
ffff800081eaa228 d mux_pll_src_cpll_gpll_p
ffff800081eaa238 d mux_aclk_bus_src_p
ffff800081eaa248 d mux_cs_src_p
ffff800081eaa260 d mux_ddrphy_p
ffff800081eaa270 d mux_pll_p
ffff800081eaa280 d mux_armclkl_p
ffff800081eaa2a0 d mux_armclkb_p
ffff800081eaa2c0 d rk3399_cru_critical_clocks
ffff800081eaa3b0 d rk3399_pmucru_critical_clocks
ffff800081eaa3d8 d mux_clk_testout2_2io_p
ffff800081eaa3e8 d mux_uart4_pmu_p
ffff800081eaa400 d mux_wifi_pmu_p
ffff800081eaa410 d mux_fclk_cm0s_pmu_ppll_p
ffff800081eaa420 d mux_24m_ppll_p
ffff800081eaa430 d mux_ppll_24m_p
ffff800081eaa440 d mux_uart3_p
ffff800081eaa458 d mux_uart2_p
ffff800081eaa470 d mux_uart1_p
ffff800081eaa488 d mux_uart0_p
ffff800081eaa4a0 d mux_i2sout_p
ffff800081eaa4b0 d mux_i2sch_p
ffff800081eaa4c8 d mux_i2s2_p
ffff800081eaa4e8 d mux_i2s1_p
ffff800081eaa508 d mux_i2s0_p
ffff800081eaa528 d mux_spdif_p
ffff800081eaa548 d mux_rmii_p
ffff800081eaa558 d mux_aclk_gmac_p
ffff800081eaa568 d mux_usbphy_480m_p
ffff800081eaa578 d mux_clk_testout2_p
ffff800081eaa588 d mux_clk_testout1_p
ffff800081eaa598 d mux_hclk_perilp1_p
ffff800081eaa5a8 d mux_fclk_cm0s_p
ffff800081eaa5b8 d mux_aclk_perilp0_p
ffff800081eaa5c8 d mux_aclk_emmc_p
ffff800081eaa5d8 d mux_pciecore_cru_phy_p
ffff800081eaa5e8 d mux_pll_src_24m_32k_cpll_gpll_p
ffff800081eaa608 d mux_pll_src_24m_pciephy_p
ffff800081eaa618 d mux_pll_src_24m_usbphy480m_p
ffff800081eaa628 d mux_clk_cif_p
ffff800081eaa638 d mux_dclk_vop1_p
ffff800081eaa648 d mux_dclk_vop0_p
ffff800081eaa658 d mux_pll_src_vpll_cpll_gpll_24m_p
ffff800081eaa678 d mux_pll_src_vpll_cpll_gpll_npll_p
ffff800081eaa698 d mux_pll_src_vpll_cpll_gpll_p
ffff800081eaa6b0 d mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p
ffff800081eaa6e0 d mux_pll_src_cpll_gpll_npll_upll_24m_p
ffff800081eaa708 d mux_pll_src_ppll_cpll_gpll_npll_p
ffff800081eaa730 d mux_pll_src_cpll_gpll_npll_usbphy480m_p
ffff800081eaa750 d mux_pll_src_cpll_gpll_npll_24m_p
ffff800081eaa770 d mux_pll_src_cpll_gpll_npll_ppll_p
ffff800081eaa790 d mux_pll_src_npll_cpll_gpll_p
ffff800081eaa7a8 d mux_pll_src_cpll_gpll_upll_p
ffff800081eaa7c0 d mux_pll_src_cpll_gpll_ppll_p
ffff800081eaa7d8 d mux_pll_src_cpll_gpll_npll_p
ffff800081eaa7f0 d mux_pll_src_cpll_gpll_p
ffff800081eaa800 d mux_aclk_perihp_p
ffff800081eaa810 d mux_cs_p
ffff800081eaa828 d mux_cci_trace_p
ffff800081eaa838 d mux_aclk_cci_p
ffff800081eaa858 d mux_ddrclk_p
ffff800081eaa878 d mux_pll_p
ffff800081eaa888 d mux_armclk
ffff800081eaa898 d clk_32k_p
ffff800081eaa8a8 d sclk_uart7_src_p
ffff800081eaa8c0 d sclk_uart6_src_p
ffff800081eaa8d8 d sclk_uart5_src_p
ffff800081eaa8f0 d sclk_uart4_src_p
ffff800081eaa908 d sclk_uart3_src_p
ffff800081eaa920 d sclk_uart2_src_p
ffff800081eaa938 d sclk_uart1_src_p
ffff800081eaa950 d sclk_uart0_src_p
ffff800081eaa968 d mclk_spdif_src_p
ffff800081eaa980 d mclk_sai_i2s1_p
ffff800081eaa990 d mclk_sai_i2s0_p
ffff800081eaa9a0 d mclk_i2s3_8ch_sai_src_p
ffff800081eaa9b8 d mclk_i2s2_2ch_sai_src_p
ffff800081eaa9d0 d mclk_i2s1_8ch_sai_src_p
ffff800081eaa9e8 d mclk_i2s0_2ch_sai_src_p
ffff800081eaaa00 d dclk_vop0_p
ffff800081eaaa10 d clk_ref_pcie_inner_phy_p
ffff800081eaaa20 d clk_i2c2_p
ffff800081eaaa40 d aclk_rkvdec_pvtmux_root_p
ffff800081eaaa50 d aclk_gpu_p
ffff800081eaaa60 d mux_600m_300m_200m_24m_p
ffff800081eaaa80 d mux_500m_300m_100m_24m_p
ffff800081eaaaa0 d mux_500m_200m_100m_24m_p
ffff800081eaaac0 d mux_339m_200m_100m_24m_p
ffff800081eaaae0 d mux_300m_200m_100m_24m_p
ffff800081eaab00 d mux_200m_100m_50m_24m_p
ffff800081eaab20 d mux_200m_100m_24m_p
ffff800081eaab38 d mux_150m_100m_24m_p
ffff800081eaab50 d mux_100m_50m_24m_p
ffff800081eaab68 d mux_gpll_cpll_xin24m_p
ffff800081eaab80 d mux_gpll_cpll_p
ffff800081eaab90 d mux_24m_32k_p
ffff800081eaaba0 d mux_pll_p
ffff800081eaaba8 d clk_mipidsi_ref_p
ffff800081eaabb8 d clk_usbphy_ref_p
ffff800081eaabc8 d clk_pipephy_ref_p
ffff800081eaabd8 d clk_pmu1_uart0_p
ffff800081eaabf0 d clk_rtc32k_pmu_p
ffff800081eaac08 d clk_uart9_p
ffff800081eaac20 d clk_uart8_p
ffff800081eaac38 d clk_uart7_p
ffff800081eaac50 d clk_uart6_p
ffff800081eaac68 d clk_uart5_p
ffff800081eaac80 d clk_uart4_p
ffff800081eaac98 d clk_uart3_p
ffff800081eaacb0 d clk_uart2_p
ffff800081eaacc8 d clk_uart1_p
ffff800081eaace0 d clk_spdif_p
ffff800081eaacf8 d mclk_sai2_out2io_p
ffff800081eaad08 d clk_sai2_p
ffff800081eaad28 d mclk_sai1_out2io_p
ffff800081eaad38 d clk_sai1_p
ffff800081eaad58 d mclk_sai0_out2io_p
ffff800081eaad68 d clk_sai0_p
ffff800081eaad88 d mux_200m_100m_50m_xin24m_p
ffff800081eaada8 d mux_200m_100m_p
ffff800081eaadb8 d mux_200m_xin24m_32k_p
ffff800081eaadd0 d mux_125m_xin24m_p
ffff800081eaade0 d mux_100m_50m_xin24m_p
ffff800081eaadf8 d mux_50m_xin24m_p
ffff800081eaae08 d mux_xin24m_32k_p
ffff800081eaae18 d vpll_dmyhpll_gpll_cpll_p
ffff800081eaae38 d gpll_cpll_xin24m_dmyhpll_p
ffff800081eaae58 d gpll_cpll_xin24m_dmyapll_p
ffff800081eaae78 d gpll_cpll_xin24m_p
ffff800081eaae90 d gpll_dmyhpll_vpll_apll_p
ffff800081eaaeb0 d gpll_cpll_vpll_dmyhpll_p
ffff800081eaaed0 d gpll_cpll_hpll_xin24m_p
ffff800081eaaef0 d gpll_cpll_pvtpll_dmyapll_p
ffff800081eaaf10 d gpll_cpll_hpll_p
ffff800081eaaf28 d gpll_cpll_p
ffff800081eaaf38 d mux_pll_p
ffff800081eaaf40 d rk3568_pmucru_critical_clocks
ffff800081eaaf58 d mux_armclk_p
ffff800081eaaf68 d rk3568_cru_critical_clocks
ffff800081eab010 d clk_rkvdec_core_p
ffff800081eab030 d aclk_rkvdec_pre_p
ffff800081eab040 d clk_pwm0_p
ffff800081eab050 d clk_mac_2top_p
ffff800081eab070 d clk_pdpmu_p
ffff800081eab080 d clk_hdmi_ref_p
ffff800081eab090 d mux_gmac1_rx_tx_p
ffff800081eab0a8 d mux_gmac1_rmii_speed_p
ffff800081eab0b8 d mux_gmac1_rgmii_speed_p
ffff800081eab0d8 d mux_gmac1_p
ffff800081eab0e8 d mux_gmac0_rx_tx_p
ffff800081eab100 d mux_gmac0_rmii_speed_p
ffff800081eab110 d mux_gmac0_rgmii_speed_p
ffff800081eab130 d mux_gmac0_p
ffff800081eab140 d clk_pciephy2_ref_p
ffff800081eab150 d clk_pciephy1_ref_p
ffff800081eab160 d clk_pciephy0_ref_p
ffff800081eab170 d clk_wifi_p
ffff800081eab180 d clk_mipidsiphy1_ref_p
ffff800081eab190 d clk_mipidsiphy0_ref_p
ffff800081eab1a0 d clk_usbphy1_ref_p
ffff800081eab1b0 d clk_usbphy0_ref_p
ffff800081eab1c0 d ppll_usb480m_cpll_gpll_p
ffff800081eab1e0 d xin24m_cpll100_p
ffff800081eab1f0 d gpll400_gpll300_gpll200_xin24m_p
ffff800081eab210 d cpll500_gpll400_gpll300_xin24m_p
ffff800081eab230 d xin24m_32k_p
ffff800081eab240 d gpll200_xin24m_cpll100_p
ffff800081eab258 d gpll100_xin24m_cpll100_p
ffff800081eab270 d gpll_cpll_usb480m_p
ffff800081eab288 d xin24m_gpll100_cpll100_p
ffff800081eab2a0 d gpll100_gpll75_cpll50_xin24m_p
ffff800081eab2c0 d gpll400_cpll333_gpll200_p
ffff800081eab2d8 d hpll_vpll_gpll_cpll_p
ffff800081eab2f8 d cpll_gpll_hpll_vpll_p
ffff800081eab318 d gpll300_cpll250_gpll100_xin24m_p
ffff800081eab338 d gpll_usb480m_xin24m_p
ffff800081eab358 d cpll_gpll_hpll_p
ffff800081eab370 d cpll333_gpll300_gpll200_p
ffff800081eab388 d clk_gmac_ptp_p
ffff800081eab3a8 d cpll125_cpll50_cpll25_xin24m_p
ffff800081eab3c8 d clk_sdmmc_p
ffff800081eab3f8 d gpll300_gpll200_gpll100_xin24m_p
ffff800081eab418 d gpll200_cpll125_p
ffff800081eab428 d aclk_pipe_p
ffff800081eab448 d cclk_emmc_p
ffff800081eab478 d gpll200_gpll150_cpll125_p
ffff800081eab490 d sclk_sfc_p
ffff800081eab4c0 d clk_nandc_p
ffff800081eab4e0 d gpll300_gpll200_gpll100_p
ffff800081eab4f8 d gpll200_gpll150_gpll100_p
ffff800081eab510 d clk_i2c_p
ffff800081eab530 d mclk_pdm_p
ffff800081eab550 d i2s3_mclkout_rx_p
ffff800081eab560 d i2s3_mclkout_tx_p
ffff800081eab570 d i2s2_mclkout_p
ffff800081eab580 d i2s1_mclkout_rx_p
ffff800081eab590 d i2s1_mclkout_tx_p
ffff800081eab5a0 d i2s0_mclkout_rx_p
ffff800081eab5b0 d i2s0_mclkout_tx_p
ffff800081eab5c0 d gpll100_gpll75_gpll50_p
ffff800081eab5d8 d gpll200_gpll150_gpll100_xin24m_p
ffff800081eab5f8 d clk_ddr1x_p
ffff800081eab608 d dpll_gpll_cpll_p
ffff800081eab620 d clk_npu_p
ffff800081eab630 d clk_npu_pre_ndft_p
ffff800081eab640 d clk_gpu_pre_mux_p
ffff800081eab650 d gpll150_gpll100_gpll75_xin24m_p
ffff800081eab670 d sclk_core_pre_p
ffff800081eab680 d apll_gpll_npll_p
ffff800081eab698 d gpll_cpll_npll_vpll_p
ffff800081eab6b8 d gpll_cpll_p
ffff800081eab6c8 d cpll_gpll_p
ffff800081eab6d8 d npll_gpll_p
ffff800081eab6e8 d gpll_cpll_npll_p
ffff800081eab700 d mpll_gpll_cpll_npll_p
ffff800081eab720 d clk_rtc32k_pmu_p
ffff800081eab738 d sclk_uart0_p
ffff800081eab750 d sclk_uart9_p
ffff800081eab768 d sclk_uart8_p
ffff800081eab780 d sclk_uart7_p
ffff800081eab798 d sclk_uart6_p
ffff800081eab7b0 d sclk_uart5_p
ffff800081eab7c8 d sclk_uart4_p
ffff800081eab7e0 d sclk_uart3_p
ffff800081eab7f8 d sclk_uart2_p
ffff800081eab810 d sclk_uart1_p
ffff800081eab828 d sclk_audpwm_p
ffff800081eab838 d mclk_spdif_8ch_p
ffff800081eab848 d clk_i2s3_2ch_rx_p
ffff800081eab868 d clk_i2s3_2ch_tx_p
ffff800081eab888 d clk_i2s2_2ch_p
ffff800081eab8a8 d clk_i2s1_8ch_rx_p
ffff800081eab8c8 d clk_i2s1_8ch_tx_p
ffff800081eab8e8 d clk_i2s0_8ch_rx_p
ffff800081eab908 d clk_i2s0_8ch_tx_p
ffff800081eab928 d mux_usb480m_phy_p
ffff800081eab938 d mux_usb480m_p
ffff800081eab950 d mux_pll_p
ffff800081eab958 d mux_armclkl_p
ffff800081eab970 d mux_armclkb_p
ffff800081eab988 d clk_aupll_ref_src_p
ffff800081eab998 d clk_cpll_ref_src_p
ffff800081eab9a8 d clk_usbphy_ref_src_p
ffff800081eab9b8 d clk_phy_ref_src_p
ffff800081eab9c8 d mux_pmu100m_24m_32k_p
ffff800081eab9e0 d mux_pmu100m_pmu50m_24m_p
ffff800081eab9f8 d mux_pmu200m_pmu100m_pmu50m_24m_p
ffff800081eaba18 d clk_ref_osc_mphy_p
ffff800081eaba30 d hclk_vi_root_p
ffff800081eaba50 d clk_ref_pcie0_phy_p
ffff800081eaba68 d sai_sclkin_freq_p
ffff800081eaba90 d clk_counter_pwm1_p
ffff800081eabac0 d clk_freq_pwm1_p
ffff800081eabaf0 d clk_uart_p
ffff800081eabb28 d dclk_vp2_p
ffff800081eabb38 d dclk_vp1_p
ffff800081eabb48 d dclk_vp0_p
ffff800081eabb58 d dclk_ebc_p
ffff800081eabb90 d clk_gmac0_ptp_ref_src_p
ffff800081eabba8 d clk_gmac1_ptp_ref_src_p
ffff800081eabbc0 d uart1_p
ffff800081eabbd0 d mclk_sai9_8ch_p
ffff800081eabbe0 d mclk_sai8_8ch_p
ffff800081eabbf0 d mclk_sai7_8ch_p
ffff800081eabc00 d mclk_sai6_8ch_p
ffff800081eabc10 d mclk_sai5_8ch_p
ffff800081eabc20 d mclk_sai4_2ch_p
ffff800081eabc38 d mclk_sai3_2ch_p
ffff800081eabc50 d mclk_sai2_2ch_p
ffff800081eabc68 d mclk_sai1_8ch_p
ffff800081eabc78 d mclk_sai0_8ch_p
ffff800081eabc90 d mux_116m_58m_24m_p
ffff800081eabca8 d mux_175m_116m_58m_24m_p
ffff800081eabcc8 d mux_350m_175m_116m_24m_p
ffff800081eabce8 d mux_600m_400m_300m_24m_p
ffff800081eabd08 d mux_500m_250m_100m_24m_p
ffff800081eabd28 d mux_400m_200m_100m_24m_p
ffff800081eabd48 d mux_200m_150m_100m_24m_p
ffff800081eabd68 d mux_200m_100m_50m_24m_p
ffff800081eabd88 d mux_150m_100m_50m_24m_p
ffff800081eabda8 d mux_100m_24m_lclk1_p
ffff800081eabdc0 d mux_100m_24m_lclk0_p
ffff800081eabdd8 d mux_100m_50m_24m_p
ffff800081eabdf0 d mux_100m_24m_p
ffff800081eabe00 d audio_frac_p
ffff800081eabe20 d audio_frac_int_p
ffff800081eabe60 d mux_24m_spll_gpll_cpll_p
ffff800081eabe80 d mux_24m_ccipvtpll_gpll_lpll_p
ffff800081eabea0 d cpll_vpll_lpll_bpll_p
ffff800081eabec0 d gpll_cpll_spll_vpll_bpll_lpll_p
ffff800081eabef0 d gpll_cpll_spll_aupll_lpll_24m_p
ffff800081eabf20 d gpll_spll_isppvtpll_bpll_lpll_p
ffff800081eabf48 d gpll_spll_aupll_bpll_lpll_p
ffff800081eabf70 d gpll_cpll_vpll_bpll_lpll_p
ffff800081eabf98 d gpll_cpll_spll_lpll_bpll_p
ffff800081eabfc0 d gpll_cpll_spll_bpll_lpll_p
ffff800081eabfe8 d gpll_cpll_spll_aupll_bpll_p
ffff800081eac010 d gpll_cpll_vpll_aupll_24m_p
ffff800081eac038 d gpll_spll_cpll_bpll_lpll_p
ffff800081eac060 d gpll_cpll_lpll_bpll_p
ffff800081eac080 d gpll_cpll_spll_bpll_p
ffff800081eac0a0 d gpll_cpll_aupll_spll_lpll_p
ffff800081eac0c8 d gpll_cpll_aupll_spll_p
ffff800081eac0e8 d gpll_cpll_aupll_24m_p
ffff800081eac108 d gpll_cpll_24m_spll_p
ffff800081eac128 d gpll_cpll_24m_p
ffff800081eac140 d gpll_cpll_aupll_p
ffff800081eac158 d gpll_spll_p
ffff800081eac168 d gpll_cpll_p
ffff800081eac178 d cpll_24m_p
ffff800081eac188 d gpll_24m_p
ffff800081eac198 d mux_24m_32k_p
ffff800081eac1a8 d mux_pll_p
ffff800081eac1b8 d mux_armclkl_p
ffff800081eac1d0 d mux_armclkb01_p
ffff800081eac1e8 d mux_armclkb23_p
ffff800081eac200 d clk_ref_pipe_phy2_p
ffff800081eac210 d clk_ref_pipe_phy1_p
ffff800081eac220 d clk_ref_pipe_phy0_p
ffff800081eac230 d mux_24m_ppll_p
ffff800081eac240 d mux_24m_ppll_spll_p
ffff800081eac258 d mclk_pdm0_p
ffff800081eac268 d hclk_pmu_cm0_root_p
ffff800081eac288 d hclk_pmu1_root_p
ffff800081eac2a8 d pmu_24m_32k_100m_src_p
ffff800081eac2c0 d pmu_100m_50m_24m_src_p
ffff800081eac2d8 d pmu_400m_24m_p
ffff800081eac2e8 d pmu_300m_24m_p
ffff800081eac2f8 d pmu_200m_100m_p
ffff800081eac308 d dclk_vop2_p
ffff800081eac320 d dclk_vop1_p
ffff800081eac338 d dclk_vop0_p
ffff800081eac350 d aclk_vop_sub_src_p
ffff800081eac360 d aclk_hdcp1_root_p
ffff800081eac378 d clk_hdmirx_aud_p
ffff800081eac388 d clk_gmac1_ptp_ref_p
ffff800081eac398 d clk_gmac0_ptp_ref_p
ffff800081eac3a8 d clk_uart9_p
ffff800081eac3c0 d clk_uart8_p
ffff800081eac3d8 d clk_uart7_p
ffff800081eac3f0 d clk_uart6_p
ffff800081eac408 d clk_uart5_p
ffff800081eac420 d clk_uart4_p
ffff800081eac438 d clk_uart3_p
ffff800081eac450 d clk_uart2_p
ffff800081eac468 d clk_uart1_p
ffff800081eac480 d clk_uart0_p
ffff800081eac498 d clk_spdif5_dp1_p
ffff800081eac4b0 d clk_spdif4_p
ffff800081eac4c8 d clk_spdif3_p
ffff800081eac4e0 d clk_spdif2_dp0_p
ffff800081eac4f8 d clk_spdif1_p
ffff800081eac510 d clk_spdif0_p
ffff800081eac528 d clk_i2s10_8ch_rx_p
ffff800081eac548 d clk_i2s9_8ch_rx_p
ffff800081eac568 d clk_i2s8_8ch_tx_p
ffff800081eac588 d clk_i2s7_8ch_rx_p
ffff800081eac5a8 d i2s6_8ch_mclkout_p
ffff800081eac5c0 d clk_i2s6_8ch_rx_p
ffff800081eac5e0 d clk_i2s6_8ch_tx_p
ffff800081eac600 d clk_i2s5_8ch_tx_p
ffff800081eac620 d clk_i2s4_8ch_tx_p
ffff800081eac640 d i2s1_8ch_mclkout_p
ffff800081eac658 d clk_i2s1_8ch_rx_p
ffff800081eac678 d clk_i2s1_8ch_tx_p
ffff800081eac698 d i2s0_8ch_mclkout_p
ffff800081eac6b0 d clk_i2s0_8ch_rx_p
ffff800081eac6d0 d clk_i2s0_8ch_tx_p
ffff800081eac6f0 d i2s3_2ch_mclkout_p
ffff800081eac700 d clk_i2s3_2ch_p
ffff800081eac720 d i2s2_2ch_mclkout_p
ffff800081eac730 d clk_i2s2_2ch_p
ffff800081eac750 d mux_400m_200m_100m_24m_p
ffff800081eac770 d mux_500m_300m_100m_24m_p
ffff800081eac790 d mux_500m_250m_100m_24m_p
ffff800081eac7b0 d mux_700m_400m_200m_24m_p
ffff800081eac7d0 d mux_300m_200m_100m_24m_p
ffff800081eac7f0 d mux_200m_100m_50m_24m_p
ffff800081eac810 d mux_150m_100m_50m_24m_p
ffff800081eac830 d mux_200m_150m_24m_p
ffff800081eac848 d mux_150m_100m_24m_p
ffff800081eac860 d mux_150m_50m_24m_p
ffff800081eac878 d mux_100m_50m_24m_p
ffff800081eac890 d mux_200m_100m_p
ffff800081eac8a0 d mux_24m_100m_p
ffff800081eac8b0 d mux_24m_32k_p
ffff800081eac8c0 d mux_24m_spll_gpll_cpll_p
ffff800081eac8e0 d gpll_cpll_npll_1000m_p
ffff800081eac900 d gpll_cpll_npll_aupll_spll_p
ffff800081eac928 d gpll_cpll_dmyaupll_npll_spll_p
ffff800081eac950 d gpll_cpll_aupll_npll_spll_p
ffff800081eac978 d gpll_cpll_v0pll_spll_p
ffff800081eac998 d gpll_cpll_v0pll_aupll_p
ffff800081eac9b8 d gpll_cpll_aupll_npll_p
ffff800081eac9d8 d gpll_cpll_aupll_spll_p
ffff800081eac9f8 d gpll_cpll_24m_spll_p
ffff800081eaca18 d gpll_cpll_npll_v0pll_p
ffff800081eaca38 d gpll_cpll_npll_p
ffff800081eaca50 d gpll_cpll_aupll_p
ffff800081eaca68 d gpll_cpll_24m_p
ffff800081eaca80 d gpll_spll_p
ffff800081eaca90 d gpll_cpll_p
ffff800081eacaa0 d gpll_lpll_p
ffff800081eacab0 d gpll_aupll_p
ffff800081eacac0 d gpll_24m_p
ffff800081eacad0 d b0pll_b1pll_lpll_gpll_p
ffff800081eacaf0 d mux_pll_p
ffff800081eacb00 d cmu_imem_info
ffff800081eacba0 d cmu_peri_info
ffff800081eacc40 d cmu_peri_gate_clks
ffff800081eacf40 d cmu_peri_div_clks
ffff800081ead0c8 d cmu_peri_mux_clks
ffff800081ead1e0 d mout_peri_i2s1_p
ffff800081ead1f0 d mout_peri_i2s0_p
ffff800081ead200 d mout_peri_disp_user_p
ffff800081ead210 d mout_peri_audio_user_p
ffff800081ead220 d mout_peri_ip_user_p
ffff800081ead230 d peri_fixed_clks
ffff800081ead258 d cmu_peri_clk_regs
ffff800081ead320 d cmu_imem_gate_clks
ffff800081ead380 d cmu_imem_mux_clks
ffff800081ead460 d mout_imem_jpeg_user_p
ffff800081ead470 d mout_imem_gic_ca5_p
ffff800081ead480 d mout_imem_gic_ca53_p
ffff800081ead490 d mout_imem_aclk_user_p
ffff800081ead4a0 d cmu_imem_clk_regs
ffff800081ead4d0 d cmu_fsys_info
ffff800081ead570 d cmu_fsys_gate_clks
ffff800081eada20 d cmu_fsys_div_clks
ffff800081eaddd8 d cmu_fsys_mux_clks
ffff800081eadef0 d mout_fsys_pll_fsys_p
ffff800081eadf00 d mout_fsys_mmc_user_p
ffff800081eadf10 d mout_fsys_bus_user_p
ffff800081eadf20 d mout_fsys_scan1_user_p
ffff800081eadf30 d mout_fsys_scan0_user_p
ffff800081eadf40 d cmu_fsys_pll_clks
ffff800081eadf78 d cmu_fsys_clk_regs
ffff800081eae0e0 d cmu_cpucl_info
ffff800081eae180 d cmu_cpucl_gate_clks
ffff800081eae240 d cmu_cpucl_div_clks
ffff800081eae400 d cpucl_ffactor_clks
ffff800081eae430 d cmu_cpucl_mux_clks
ffff800081eae4d8 d mout_clk_cpucl_pll_p
ffff800081eae4e8 d mout_pll_cpucl_p
ffff800081eae4f8 d mout_clkcmu_cpucl_switch_user_p
ffff800081eae508 d cmu_cpucl_pll_clks
ffff800081eae540 d cmu_cpucl_clk_regs
ffff800081eae5b8 d cmu_core_info
ffff800081eae658 d cmu_core_div_clks
ffff800081eae690 d cmu_core_mux_clks
ffff800081eae700 d mout_clk_core_dlp_user_p
ffff800081eae710 d mout_clk_core_aclk_user_p
ffff800081eae720 d cmu_core_clk_regs
ffff800081eae738 d cmu_bus_info
ffff800081eae7d8 d cmu_bus_div_clks
ffff800081eae810 d cmu_bus_mux_clks
ffff800081eae880 d mout_clk_bus_dlp_user_p
ffff800081eae890 d mout_clk_bus_aclk_user_p
ffff800081eae8a0 d cmu_bus_clk_regs
ffff800081eae8b8 d cmu_cmu_info
ffff800081eae958 d cmu_cmu_div_clks
ffff800081eaf100 d cmu_cmu_mux_clks
ffff800081eaf790 d cmu_fixed_factor_clks
ffff800081eaf7c0 d mout_clkcmu_pll_audio_p
ffff800081eaf7d0 d mout_clkcmu_pll_shared1_p
ffff800081eaf7e0 d mout_clkcmu_pll_shared0_p
ffff800081eaf7f0 d mout_clkcmu_vpp_core_p
ffff800081eaf810 d mout_clkcmu_vip1_core_p
ffff800081eaf830 d mout_clkcmu_vip0_core_p
ffff800081eaf850 d mout_clkcmu_vio_core_p
ffff800081eaf870 d mout_clkcmu_vca_od_p
ffff800081eaf890 d mout_clkcmu_vca_ace_p
ffff800081eaf8b0 d mout_clkcmu_trfm_core_p
ffff800081eaf8d0 d mout_clkcmu_rsp_core_p
ffff800081eaf8f0 d mout_clkcmu_peri_ip_p
ffff800081eaf910 d mout_clkcmu_peri_disp_p
ffff800081eaf930 d mout_clkcmu_mif_busp_p
ffff800081eaf950 d mout_clkcmu_mif_switch_p
ffff800081eaf970 d mout_clkcmu_2d_p
ffff800081eaf990 d mout_clkcmu_3d_p
ffff800081eaf9b0 d mout_clkcmu_dlp_core_p
ffff800081eaf9d0 d mout_clkcmu_cdc_core_p
ffff800081eaf9f0 d mout_clkcmu_imem_jpeg_p
ffff800081eafa10 d mout_clkcmu_imem_imem_p
ffff800081eafa30 d mout_clkcmu_fsys_scan1_p
ffff800081eafa40 d mout_clkcmu_fsys_scan0_p
ffff800081eafa50 d mout_clkcmu_fsys_ip_p
ffff800081eafa70 d mout_clkcmu_fsys_bus_p
ffff800081eafa90 d mout_clkcmu_cpucl_switch_p
ffff800081eafab0 d mout_clkcmu_core_dlp_p
ffff800081eafad0 d mout_clkcmu_core_bus_p
ffff800081eafaf0 d mout_clkcmu_bus_dlp_p
ffff800081eafb10 d mout_clkcmu_bus_bus_p
ffff800081eafb30 d cmu_cmu_pll_clks
ffff800081eafbd8 d artpec8_pll_audio_rates
ffff800081eafcb0 d cmu_cmu_clk_regs
ffff800081eafed0 d atlas_cmu_info
ffff800081eaff70 d apollo_cmu_info
ffff800081eb0010 d bus2_cmu_info
ffff800081eb00b0 d bus1_cmu_info
ffff800081eb0150 d bus0_cmu_info
ffff800081eb01f0 d peris_cmu_info
ffff800081eb0290 d peric_cmu_info
ffff800081eb0330 d mif_cmu_info
ffff800081eb03d0 d cpif_cmu_info
ffff800081eb0470 d top_cmu_info
ffff800081eb0510 d imem_cmu_info
ffff800081eb05b0 d imem_gate_clks
ffff800081eb0610 d imem_clk_regs
ffff800081eb0620 d cam1_cmu_info
ffff800081eb06c0 d cam1_gate_clks
ffff800081eb1740 d cam1_div_clks
ffff800081eb1970 d cam1_mux_clks
ffff800081eb1c48 d cam1_fixed_clks
ffff800081eb1c70 d mout_aclk_lite_c_a_p
ffff800081eb1c80 d mout_aclk_lite_c_b_p
ffff800081eb1c90 d mout_aclk_fd_a_p
ffff800081eb1ca0 d mout_aclk_fd_b_p
ffff800081eb1cb0 d mout_aclk_csis2_a_p
ffff800081eb1cc0 d mout_aclk_csis2_b_p
ffff800081eb1cd0 d mout_phyclk_rxbyteclkhs0_s2b_user_p
ffff800081eb1ce0 d mout_aclk_cam1_552_user_p
ffff800081eb1cf0 d mout_aclk_cam1_400_user_p
ffff800081eb1d00 d mout_aclk_cam1_333_user_p
ffff800081eb1d10 d mout_sclk_isp_spi0_user_p
ffff800081eb1d20 d mout_sclk_isp_spi1_user_p
ffff800081eb1d30 d mout_sclk_isp_uart_user_p
ffff800081eb1d40 d cam1_clk_regs
ffff800081eb1dc8 d cam0_cmu_info
ffff800081eb1e68 d cam0_gate_clks
ffff800081eb2e28 d cam0_div_clks
ffff800081eb3218 d cam0_mux_clks
ffff800081eb3800 d cam0_fixed_clks
ffff800081eb3850 d mout_sclk_pixelasync_lite_c_init_a_p
ffff800081eb3860 d mout_sclk_pixelasync_lite_c_init_b_p
ffff800081eb3870 d mout_sclk_pixelasync_lite_c_a_p
ffff800081eb3880 d mout_sclk_pixelasync_lite_c_b_p
ffff800081eb3890 d mout_sclk_lite_freecnt_a_p
ffff800081eb38a0 d mout_sclk_lite_freecnt_b_p
ffff800081eb38b0 d mout_sclk_lite_freecnt_c_p
ffff800081eb38c0 d mout_aclk_3aa0_a_p
ffff800081eb38d0 d mout_aclk_3aa0_b_p
ffff800081eb38e0 d mout_aclk_3aa1_a_p
ffff800081eb38f0 d mout_aclk_3aa1_b_p
ffff800081eb3900 d mout_aclk_csis0_a_p
ffff800081eb3910 d mout_aclk_csis0_b_p
ffff800081eb3920 d mout_aclk_csis1_a_p
ffff800081eb3930 d mout_aclk_csis1_b_p
ffff800081eb3940 d mout_aclk_cam0_400_p
ffff800081eb3950 d mout_aclk_lite_a_a_p
ffff800081eb3960 d mout_aclk_lite_a_b_p
ffff800081eb3970 d mout_aclk_lite_b_a_p
ffff800081eb3980 d mout_aclk_lite_b_b_p
ffff800081eb3990 d mout_aclk_lite_d_a_p
ffff800081eb39a0 d mout_aclk_lite_d_b_p
ffff800081eb39b0 d mout_phyclk_rxbyteclkhs0_s2a_user_p
ffff800081eb39c0 d mout_phyclk_rxbyteclkhs0_s4_user_p
ffff800081eb39d0 d mout_aclk_cam0_552_user_p
ffff800081eb39e0 d mout_aclk_cam0_400_user_p
ffff800081eb39f0 d mout_aclk_cam0_333_user_p
ffff800081eb3a00 d cam0_clk_regs
ffff800081eb3ac0 d isp_cmu_info
ffff800081eb3b60 d isp_gate_clks
ffff800081eb48b0 d isp_div_clks
ffff800081eb4990 d isp_mux_clks
ffff800081eb4a00 d mout_aclk_isp_400_user_p
ffff800081eb4a10 d mout_aclk_isp_dis_400_user_p
ffff800081eb4a20 d isp_clk_regs
ffff800081eb4a80 d hevc_cmu_info
ffff800081eb4b20 d hevc_gate_clks
ffff800081eb4e20 d hevc_div_clks
ffff800081eb4e58 d hevc_mux_clks
ffff800081eb4e90 d mout_aclk_hevc_400_user_p
ffff800081eb4ea0 d hevc_clk_regs
ffff800081eb4ef0 d mfc_cmu_info
ffff800081eb4f90 d mfc_gate_clks
ffff800081eb5290 d mfc_div_clks
ffff800081eb52c8 d mfc_mux_clks
ffff800081eb5300 d mout_aclk_mfc_400_user_p
ffff800081eb5310 d mfc_clk_regs
ffff800081eb5360 d mscl_cmu_info
ffff800081eb5400 d mscl_gate_clks
ffff800081eb58b0 d mscl_div_clks
ffff800081eb58e8 d mscl_mux_clks
ffff800081eb5990 d mout_sclk_jpeg_p
ffff800081eb59a0 d mout_aclk_mscl_400_user_p
ffff800081eb59b0 d mout_sclk_jpeg_user_p
ffff800081eb59c0 d mscl_clk_regs
ffff800081eb5a58 d atlas_cpu_clks
ffff800081eb5a88 d exynos5433_atlasclk_d
ffff800081eb5c08 d atlas_gate_clks
ffff800081eb6088 d atlas_div_clks
ffff800081eb6280 d atlas_mux_clks
ffff800081eb6328 d atlas_pll_clks
ffff800081eb6360 d mout_atlas_p
ffff800081eb6370 d mout_bus_pll_atlas_user_p
ffff800081eb6380 d mout_atlas_pll_p
ffff800081eb6390 d atlas_clk_regs
ffff800081eb6460 d apollo_cpu_clks
ffff800081eb6490 d exynos5433_apolloclk_d
ffff800081eb6598 d apollo_gate_clks
ffff800081eb67d8 d apollo_div_clks
ffff800081eb69d0 d apollo_mux_clks
ffff800081eb6a78 d apollo_pll_clks
ffff800081eb6ab0 d mout_apollo_p
ffff800081eb6ac0 d mout_bus_pll_apollo_user_p
ffff800081eb6ad0 d mout_apollo_pll_p
ffff800081eb6ae0 d apollo_clk_regs
ffff800081eb6bb0 d gscl_cmu_info
ffff800081eb6c50 d gscl_gate_clks
ffff800081eb7130 d gscl_mux_clks
ffff800081eb71a0 d aclk_gscl_333_user_p
ffff800081eb71b0 d aclk_gscl_111_user_p
ffff800081eb71c0 d gscl_clk_regs
ffff800081eb7238 d g3d_cmu_info
ffff800081eb72d8 d g3d_gate_clks
ffff800081eb7548 d g3d_div_clks
ffff800081eb75f0 d g3d_mux_clks
ffff800081eb7660 d g3d_pll_clks
ffff800081eb7698 d mout_g3d_pll_p
ffff800081eb76a8 d mout_aclk_g3d_400_p
ffff800081eb76b8 d g3d_clk_regs
ffff800081eb7738 d bus2_gate_clks
ffff800081eb7888 d bus2_div_clks
ffff800081eb78c0 d bus2_mux_clks
ffff800081eb78f8 d bus1_gate_clks
ffff800081eb7a18 d bus1_div_clks
ffff800081eb7a50 d bus0_gate_clks
ffff800081eb7b70 d bus0_div_clks
ffff800081eb7ba8 d bus2_clk_regs
ffff800081eb7be0 d bus01_clk_regs
ffff800081eb7c08 d mout_aclk_bus2_400_p
ffff800081eb7c18 d aud_cmu_info
ffff800081eb7cb8 d aud_gate_clks
ffff800081eb8258 d aud_div_clks
ffff800081eb8418 d aud_mux_clks
ffff800081eb84c0 d aud_fixed_clks
ffff800081eb8538 d mout_sclk_aud_pcm_p
ffff800081eb8548 d mout_aud_pll_user_aud_p
ffff800081eb8558 d aud_clk_regs
ffff800081eb85b8 d disp_cmu_info
ffff800081eb8658 d disp_gate_clks
ffff800081eb9348 d disp_div_clks
ffff800081eb94d0 d disp_mux_clks
ffff800081eb9a10 d disp_fixed_clks
ffff800081eb9b00 d disp_fixed_factor_clks
ffff800081eb9b60 d disp_pll_clks
ffff800081eb9b98 d mout_sclk_decon_tv_vclk_b_disp_p
ffff800081eb9ba8 d mout_sclk_decon_tv_vclk_c_disp_p
ffff800081eb9bb8 d mout_sclk_dsim1_b_disp_p
ffff800081eb9bc8 d mout_sclk_decon_eclk_p
ffff800081eb9bd8 d mout_sclk_decon_vclk_p
ffff800081eb9be8 d mout_sclk_decon_tv_eclk_p
ffff800081eb9bf8 d mout_sclk_dsim0_p
ffff800081eb9c08 d mout_phyclk_hdmiphy_pixel_clko_user_p
ffff800081eb9c18 d mout_phyclk_hdmiphy_tmds_clko_user_p
ffff800081eb9c28 d mout_phyclk_mipidphy0_rxclkesc0_user_p
ffff800081eb9c38 d mout_phyclk_mipidphy0_bitclkdiv8_user_p
ffff800081eb9c48 d mout_phyclk_mipidphy1_rxclkesc0_user_p
ffff800081eb9c58 d mout_phyclk_mipidphy1_bitclkdiv8_user_p
ffff800081eb9c68 d mout_aclk_disp_333_user_p
ffff800081eb9c78 d mout_sclk_decon_tv_vlkc_user_p
ffff800081eb9c88 d mout_sclk_decon_eclk_user_p
ffff800081eb9c98 d mout_sclk_decon_vclk_user_p
ffff800081eb9ca8 d mout_sclk_decon_tv_eclk_user_p
ffff800081eb9cb8 d mout_sclk_dsd_user_p
ffff800081eb9cc8 d mout_sclk_dsim0_user_p
ffff800081eb9cd8 d mout_sclk_dsim1_user_p
ffff800081eb9ce8 d mout_disp_pll_p
ffff800081eb9cf8 d disp_clk_regs
ffff800081eb9dc0 d g2d_cmu_info
ffff800081eb9e60 d g2d_gate_clks
ffff800081eba2b0 d g2d_div_clks
ffff800081eba2e8 d g2d_mux_clks
ffff800081eba358 d mout_aclk_g2d_400_user_p
ffff800081eba368 d mout_aclk_g2d_266_user_p
ffff800081eba378 d g2d_clk_regs
ffff800081eba3c8 d fsys_cmu_info
ffff800081eba468 d fsys_gate_clks
ffff800081ebb0c8 d fsys_mux_clks
ffff800081ebb5d0 d fsys_fixed_clks
ffff800081ebb7d8 d fsys_clk_regs
ffff800081ebb868 d mout_sclk_mphy_p
ffff800081ebb878 d mout_phyclk_lli_mphy_to_ufs_user_p
ffff800081ebb888 d mout_phyclk_ufs_tx0_symbol_user_p
ffff800081ebb898 d mout_phyclk_ufs_tx1_symbol_user_p
ffff800081ebb8a8 d mout_phyclk_ufs_rx0_symbol_user_p
ffff800081ebb8b8 d mout_phyclk_ufs_rx1_symbol_user_p
ffff800081ebb8c8 d mout_phyclk_usbdrd30_udrd30_phyclock_user_p
ffff800081ebb8d8 d mout_phyclk_usbdrd30_udrd30_pipe_pclk_p
ffff800081ebb8e8 d mout_phyclk_usbhost20_phy_freeclk_user_p
ffff800081ebb8f8 d mout_phyclk_usbhost20_phy_phyclock_user_p
ffff800081ebb908 d mout_phyclk_usbhost20_phy_clk48mohci_user_p
ffff800081ebb918 d mout_phyclk_usbhost20_phy_hsic1_p
ffff800081ebb928 d mout_phyclk_usbhost30_uhost30_phyclock_user_p
ffff800081ebb938 d mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p
ffff800081ebb948 d mout_sclk_usbdrd30_user_p
ffff800081ebb958 d mout_sclk_usbhost30_user_p
ffff800081ebb968 d mout_sclk_mmc0_user_p
ffff800081ebb978 d mout_sclk_mmc1_user_p
ffff800081ebb988 d mout_sclk_mmc2_user_p
ffff800081ebb998 d mout_sclk_ufsunipro_user_p
ffff800081ebb9a8 d mout_sclk_pcie_100_user_p
ffff800081ebb9b8 d mout_aclk_fsys_200_user_p
ffff800081ebb9c8 d mout_sclk_ufs_mphy_user_p
ffff800081ebb9d8 d peris_gate_clks
ffff800081ebc188 d peris_clk_regs
ffff800081ebc250 d peric_gate_clks
ffff800081ebce80 d peric_div_clks
ffff800081ebcef0 d peric_clk_regs
ffff800081ebcf30 d mif_gate_clks
ffff800081ebe2e0 d mif_div_clks
ffff800081ebe778 d mif_mux_clks
ffff800081ebf000 d mif_fixed_factor_clks
ffff800081ebf0c0 d mout_sclk_dsim1_b_p
ffff800081ebf0d0 d mout_sclk_dsim1_c_p
ffff800081ebf0e0 d mout_sclk_decon_tv_vclk_b_p
ffff800081ebf0f0 d mout_sclk_decon_tv_vclk_c_p
ffff800081ebf100 d mout_sclk_dsim0_b_p
ffff800081ebf110 d mout_sclk_dsim0_c_p
ffff800081ebf120 d mout_sclk_dsd_a_p
ffff800081ebf130 d mout_sclk_dsd_b_p
ffff800081ebf140 d mout_sclk_dsd_c_p
ffff800081ebf150 d mout_sclk_decon_tv_eclk_b_p
ffff800081ebf160 d mout_sclk_decon_tv_eclk_c_p
ffff800081ebf170 d mout_sclk_decon_eclk_b_p
ffff800081ebf180 d mout_sclk_decon_eclk_c_p
ffff800081ebf190 d mout_sclk_decon_p
ffff800081ebf1a0 d mout_sclk_decon_vclk_b_p
ffff800081ebf1b0 d mout_sclk_decon_vclk_c_p
ffff800081ebf1c0 d mout_aclk_disp_333_a_p
ffff800081ebf1d0 d mout_aclk_disp_333_b_p
ffff800081ebf1e0 d mout_aclk_mifnm_400_p
ffff800081ebf1f0 d mout_aclk_mifnm_200_p
ffff800081ebf200 d mout_clkm_phy_b_p
ffff800081ebf210 d mout_clk2x_phy_a_p
ffff800081ebf220 d mout_clk2x_phy_b_p
ffff800081ebf230 d mout_clk2x_phy_c_p
ffff800081ebf240 d mout_mem0_pll_p
ffff800081ebf250 d mout_mem1_pll_p
ffff800081ebf260 d mout_bus_pll_p
ffff800081ebf270 d mout_mfc_pll_p
ffff800081ebf280 d mout_mem0_pll_div2_p
ffff800081ebf290 d mout_mem1_pll_div2_p
ffff800081ebf2a0 d mout_bus_pll_div2_p
ffff800081ebf2b0 d mout_mfc_pll_div2_p
ffff800081ebf2c0 d mif_pll_clks
ffff800081ebf3a0 d mif_clk_regs
ffff800081ebf590 d cpif_gate_clks
ffff800081ebf5f0 d cpif_div_clks
ffff800081ebf628 d cpif_mux_clks
ffff800081ebf660 d cpif_pll_clks
ffff800081ebf698 d mout_mphy_pll_p
ffff800081ebf6a8 d cpif_clk_regs
ffff800081ebf6e0 d top_pll_clks
ffff800081ebf750 d exynos5433_aud_pll_rates
ffff800081ebf8e0 d exynos5433_pll_rates
ffff800081ebffc8 d top_gate_clks
ffff800081ec09e8 d top_div_clks
ffff800081ec1820 d top_mux_clks
ffff800081ec2428 d top_fixed_clks
ffff800081ec2590 d top_fixed_factor_clks
ffff800081ec25c0 d mout_sclk_hdmi_spdif_p
ffff800081ec25d0 d mout_sclk_audio0_p
ffff800081ec25e8 d mout_sclk_audio1_p
ffff800081ec2600 d mout_sclk_spdif_p
ffff800081ec2620 d mout_sclk_mmc0_b_p
ffff800081ec2630 d mout_sclk_mmc0_c_p
ffff800081ec2640 d mout_sclk_mmc0_d_p
ffff800081ec2650 d mout_sclk_mmc1_b_p
ffff800081ec2660 d mout_sclk_mmc2_b_p
ffff800081ec2670 d mout_sclk_jpeg_b_p
ffff800081ec2680 d mout_sclk_jpeg_c_p
ffff800081ec2690 d mout_aclk_g2d_400_b_p
ffff800081ec26a0 d mout_aclk_mscl_b_p
ffff800081ec26b0 d mout_bus_mphy_pll_user_p
ffff800081ec26c0 d mout_aclk_mfc_400_a_p
ffff800081ec26d0 d mout_aclk_mfc_400_b_p
ffff800081ec26e0 d mout_aclk_mfc_400_c_p
ffff800081ec26f0 d mout_aclk_cam1_552_a_p
ffff800081ec2700 d mout_aclk_cam1_552_b_p
ffff800081ec2710 d mout_mfc_bus_pll_user_p
ffff800081ec2720 d mout_bus_mfc_pll_user_p
ffff800081ec2730 d mout_mphy_pll_user_t_p
ffff800081ec2740 d mout_bus_pll_user_t_p
ffff800081ec2750 d mout_bus_pll_user_p
ffff800081ec2760 d mout_mfc_pll_user_p
ffff800081ec2770 d mout_mphy_pll_user_p
ffff800081ec2780 d mout_aud_pll_user_p
ffff800081ec2790 d mout_isp_pll_p
ffff800081ec27a0 d mout_aud_pll_p
ffff800081ec27b0 d top_clk_regs
ffff800081ec2990 d peris_cmu_info
ffff800081ec2a30 d alive_cmu_info
ffff800081ec2ad0 d top_cmu_info
ffff800081ec2b70 d vts_cmu_info
ffff800081ec2c10 d vts_fixed_clks
ffff800081ec2c88 d vts_div_clks
ffff800081ec2e48 d vts_mux_clks
ffff800081ec2f98 d mout_clkvts_dmic_pad_p
ffff800081ec2fa8 d mout_clkvts_noc_p
ffff800081ec2fb8 d mout_clkvts_aud_dmic1_p
ffff800081ec2ff8 d mout_clkcmu_vts_dmic_user_p
ffff800081ec3008 d mout_clkalive_vts_rco_user_p
ffff800081ec3010 d mout_clkalive_vts_noc_user_p
ffff800081ec3018 d vts_clk_regs
ffff800081ec3258 d ufs_cmu_info
ffff800081ec32f8 d ufs_mux_clks
ffff800081ec33a0 d mout_clkcmu_ufs_ufs_embd_user_p
ffff800081ec33b0 d mout_clkcmu_ufs_noc_user_p
ffff800081ec33c0 d mout_clkcmu_ufs_mmc_card_user_p
ffff800081ec33d0 d ufs_clk_regs
ffff800081ec34e0 d peric2_cmu_info
ffff800081ec3580 d peric2_div_clks
ffff800081ec3820 d peric2_mux_clks
ffff800081ec3b68 d mout_peric2_usi11_p
ffff800081ec3b88 d mout_peric2_usi06_p
ffff800081ec3ba8 d mout_peric2_usi05_p
ffff800081ec3bc8 d mout_peric2_usi03_p
ffff800081ec3be8 d mout_peric2_usi02_p
ffff800081ec3c08 d mout_peric2_usi01_spi_i2c_p
ffff800081ec3c28 d mout_peric2_usi01_p
ffff800081ec3c48 d mout_peric2_usi00_spi_i2c_p
ffff800081ec3c68 d mout_peric2_usi00_p
ffff800081ec3c88 d mout_peric2_uart_dbg_p
ffff800081ec3ca8 d mout_peric2_spi_ms_ctrl_p
ffff800081ec3cc8 d mout_peric2_i2c_p
ffff800081ec3ce8 d mout_peric2_noc_user_p
ffff800081ec3cf8 d mout_peric2_ip1_user_p
ffff800081ec3d08 d mout_peric2_ip0_user_p
ffff800081ec3d18 d peric2_clk_regs
ffff800081ec4050 d peric1_cmu_info
ffff800081ec40f0 d peric1_div_clks
ffff800081ec42e8 d peric1_mux_clks
ffff800081ec4588 d mout_peric1_usi10_p
ffff800081ec45a8 d mout_peric1_usi09_p
ffff800081ec45c8 d mout_peric1_usi08_spi_i2c_p
ffff800081ec45e8 d mout_peric1_usi08_p
ffff800081ec4608 d mout_peric1_usi07_spi_i2c_p
ffff800081ec4628 d mout_peric1_usi07_p
ffff800081ec4648 d mout_peric1_uart_bt_p
ffff800081ec4668 d mout_peric1_spi_ms_ctrl_p
ffff800081ec4688 d mout_peric1_i2c_p
ffff800081ec46a8 d mout_peric1_noc_user_p
ffff800081ec46b8 d mout_peric1_ip1_user_p
ffff800081ec46c8 d mout_peric1_ip0_user_p
ffff800081ec46d8 d peric1_clk_regs
ffff800081ec48c0 d peric0_cmu_info
ffff800081ec4960 d peric0_div_clks
ffff800081ec49d0 d peric0_mux_clks
ffff800081ec4ae8 d mout_peric0_usi04_p
ffff800081ec4b08 d mout_peric0_i2c_p
ffff800081ec4b28 d mout_peric0_noc_user_p
ffff800081ec4b38 d mout_peric0_ip1_user_p
ffff800081ec4b48 d mout_peric0_ip0_user_p
ffff800081ec4b58 d peric0_clk_regs
ffff800081ec4c50 d hsi0_cmu_info
ffff800081ec4cf0 d hsi0_div_clks
ffff800081ec4d28 d hsi0_mux_clks
ffff800081ec4eb0 d mout_mux_clk_hsi0_usb32drd_p
ffff800081ec4ec0 d mout_mux_clk_hsi0_rtcclk_p
ffff800081ec4ed0 d mout_mux_clk_hsi0_noc_p
ffff800081ec4ed8 d mout_clkcmu_hsi0_usb32drd_user_p
ffff800081ec4ee8 d mout_clkcmu_hsi0_noc_user_p
ffff800081ec4ef8 d mout_clkcmu_hsi0_dposc_user_p
ffff800081ec4f08 d mout_clkcmu_hsi0_dpgtc_user_p
ffff800081ec4f18 d hsi0_clk_regs
ffff800081ec5090 d cmgp_cmu_info
ffff800081ec5130 d cmgp_div_clks
ffff800081ec5398 d cmgp_mux_clks
ffff800081ec5670 d mout_cmgp_usi6_p
ffff800081ec5680 d mout_cmgp_usi5_p
ffff800081ec5690 d mout_cmgp_usi4_p
ffff800081ec56a0 d mout_cmgp_usi3_p
ffff800081ec56b0 d mout_cmgp_usi2_p
ffff800081ec56c0 d mout_cmgp_usi1_p
ffff800081ec56d0 d mout_cmgp_usi0_p
ffff800081ec56e0 d mout_cmgp_spi_ms_ctrl_p
ffff800081ec56f0 d mout_cmgp_spi_i2c1_p
ffff800081ec5700 d mout_cmgp_spi_i2c0_p
ffff800081ec5710 d mout_cmgp_i2c_p
ffff800081ec5720 d mout_cmgp_clkalive_peri_user_p
ffff800081ec5730 d mout_cmgp_clkalive_noc_user_p
ffff800081ec5740 d cmgp_clk_regs
ffff800081ec59d0 d peris_fixed_factor_clks
ffff800081ec5a30 d peris_mux_clks
ffff800081ec5ad8 d mout_peris_gic_p
ffff800081ec5ae8 d mout_peris_noc_user_p
ffff800081ec5af8 d mout_peris_gic_user_p
ffff800081ec5b08 d peris_clk_regs
ffff800081ec5c18 d alive_fixed_clks
ffff800081ec5c90 d alive_div_clks
ffff800081ec5fd8 d alive_mux_clks
ffff800081ec6438 d mout_alive_dsp_noc_p
ffff800081ec6458 d mout_alive_csis_noc_p
ffff800081ec6478 d mout_alive_timer_p
ffff800081ec6488 d mout_alive_spmi_p
ffff800081ec64a8 d mout_alive_pmu_sub_p
ffff800081ec64c8 d mout_alive_noc_p
ffff800081ec64e8 d mout_alive_dbgcore_uart_p
ffff800081ec6508 d mout_alive_ufd_noc_p
ffff800081ec6528 d mout_alive_sdma_noc_p
ffff800081ec6548 d mout_alive_gnss_noc_p
ffff800081ec6558 d mout_alive_gnpu_noc_p
ffff800081ec6578 d mout_alive_chubvts_noc_p
ffff800081ec6598 d mout_alive_dnc_noc_p
ffff800081ec65b8 d mout_alive_dbgcore_noc_p
ffff800081ec65d8 d mout_alive_cmgp_peri_p
ffff800081ec65f8 d mout_alive_cmgp_noc_p
ffff800081ec6618 d mout_alive_chub_peri_p
ffff800081ec6638 d mout_rco_alive_user_p
ffff800081ec6648 d mout_alive_rco_spmi_user_p
ffff800081ec6658 d mout_alive_noc_user_p
ffff800081ec6668 d alive_clk_regs
ffff800081ec6a78 d top_fixed_factor_clks
ffff800081ec6ec8 d top_div_clks
ffff800081ec85f8 d top_mux_clks
ffff800081ec9e78 d top_pll_clks
ffff800081eca000 d mout_cmu_mux_ufs_noc_p
ffff800081eca020 d mout_cmu_mux_m2m_frc_p
ffff800081eca060 d mout_cmu_mcsc_noc_p
ffff800081eca0a0 d mout_cmu_mcsc_mcsc_p
ffff800081eca0e0 d mout_cmu_m2m_frc_p
ffff800081eca120 d mout_cmu_mux_cp_shared2_clk_p
ffff800081eca140 d mout_cmu_mux_cp_shared1_clk_p
ffff800081eca160 d mout_cmu_mux_cp_shared0_clk_p
ffff800081eca180 d mout_cmu_mux_cp_hispeedy_clk_p
ffff800081eca190 d mout_cmu_mux_cmu_cmuref_p
ffff800081eca1a0 d mout_cmu_mux_yuvp_noc_p
ffff800081eca1e0 d mout_cmu_mux_vts_dmic_p
ffff800081eca200 d mout_cmu_mux_ssp_noc_p
ffff800081eca220 d mout_cmu_mux_sdma_noc_p
ffff800081eca260 d mout_cmu_mux_peris_noc_p
ffff800081eca270 d mout_cmu_mux_peris_gic_p
ffff800081eca280 d mout_cmu_mux_peric2_noc_p
ffff800081eca290 d mout_cmu_mux_peric2_ip1_p
ffff800081eca2b0 d mout_cmu_mux_peric2_ip0_p
ffff800081eca2d0 d mout_cmu_mux_peric1_noc_p
ffff800081eca2e0 d mout_cmu_mux_peric1_ip1_p
ffff800081eca300 d mout_cmu_mux_peric1_ip0_p
ffff800081eca320 d mout_cmu_mux_peric0_noc_p
ffff800081eca330 d mout_cmu_mux_peric0_ip1_p
ffff800081eca350 d mout_cmu_mux_peric0_ip0_p
ffff800081eca370 d mout_cmu_mux_nocl1c_noc_p
ffff800081eca3b0 d mout_cmu_mux_nocl1b_noc1_p
ffff800081eca3d0 d mout_cmu_mux_nocl1b_noc0_p
ffff800081eca410 d mout_cmu_mux_nocl1a_noc_p
ffff800081eca450 d mout_cmu_mux_nocl0_noc_p
ffff800081eca490 d mout_cmu_mux_mif_switch_p
ffff800081eca4d0 d mout_cmu_mux_mif_nocp_p
ffff800081eca4f0 d mout_cmu_mux_mfc1_mfc1_p
ffff800081eca530 d mout_cmu_mux_mfc0_wfd_p
ffff800081eca570 d mout_cmu_mux_mfc0_mfc0_p
ffff800081eca5b0 d mout_cmu_mux_mcsc_noc_p
ffff800081eca5f0 d mout_cmu_mux_mcsc_mcsc_p
ffff800081eca630 d mout_cmu_mux_m2m_noc_p
ffff800081eca670 d mout_cmu_mux_lme_noc_p
ffff800081eca6b0 d mout_cmu_mux_lme_lme_p
ffff800081eca6f0 d mout_cmu_mux_ufs_ufs_embd_p
ffff800081eca710 d mout_cmu_mux_hsi1_pcie_p
ffff800081eca720 d mout_cmu_mux_hsi1_noc_p
ffff800081eca740 d mout_cmu_mux_ufs_mmc_card_p
ffff800081eca760 d mout_cmu_mux_hsi0_usb32drd_p
ffff800081eca780 d mout_cmu_mux_hsi0_noc_p
ffff800081eca7a0 d mout_cmu_mux_hsi0_dposc_p
ffff800081eca7b0 d mout_cmu_mux_hsi0_dpgtc_p
ffff800081eca7d0 d mout_cmu_mux_gnpu_noc_p
ffff800081eca810 d mout_cmu_mux_g3d_switch_p
ffff800081eca850 d mout_cmu_mux_g3d_nocp_p
ffff800081eca870 d mout_cmu_mux_dsu_switch_p
ffff800081eca8b0 d mout_cmu_mux_dsp_noc_p
ffff800081eca8f0 d mout_cmu_mux_dpuf_alt_p
ffff800081eca930 d mout_cmu_mux_dpuf_p
ffff800081eca970 d mout_cmu_mux_dpub_dsim_p
ffff800081eca990 d mout_cmu_mux_dpub_alt_p
ffff800081eca9d0 d mout_cmu_mux_dpub_p
ffff800081ecaa10 d mout_cmu_mux_dnc_noc_p
ffff800081ecaa50 d mout_cmu_mux_cstat_noc_p
ffff800081ecaa90 d mout_cmu_mux_csis_ois_mcu_p
ffff800081ecaaa0 d mout_cmu_mux_csis_noc_p
ffff800081ecaae0 d mout_cmu_mux_csis_dcphy_p
ffff800081ecab00 d mout_cmu_mux_cpucl2_switch_p
ffff800081ecab40 d mout_cmu_mux_cpucl1_switch_p
ffff800081ecab80 d mout_cmu_mux_cpucl0_switch_p
ffff800081ecabc0 d mout_cmu_mux_cpucl0_nocp_p
ffff800081ecabe0 d mout_cmu_mux_cpucl0_dbg_noc_p
ffff800081ecac00 d mout_cmu_mux_cmu_boost_mif_p
ffff800081ecac20 d mout_cmu_mux_cmu_boost_cpu_p
ffff800081ecac40 d mout_cmu_mux_cmu_boost_cam_p
ffff800081ecac60 d mout_cmu_mux_cmu_boost_p
ffff800081ecac80 d mout_cmu_mux_cis_clk7_p
ffff800081ecac90 d mout_cmu_mux_cis_clk6_p
ffff800081ecaca0 d mout_cmu_mux_cis_clk5_p
ffff800081ecacb0 d mout_cmu_mux_cis_clk4_p
ffff800081ecacc0 d mout_cmu_mux_cis_clk3_p
ffff800081ecacd0 d mout_cmu_mux_cis_clk2_p
ffff800081ecace0 d mout_cmu_mux_cis_clk1_p
ffff800081ecacf0 d mout_cmu_mux_cis_clk0_p
ffff800081ecad00 d mout_cmu_mux_brp_noc_p
ffff800081ecad40 d mout_cmu_mux_aud_noc_p
ffff800081ecad80 d mout_cmu_mux_aud_cpu_p
ffff800081ecadc0 d mout_cmu_mux_aud_audif1_p
ffff800081ecae00 d mout_cmu_mux_aud_audif0_p
ffff800081ecae40 d mout_cmu_mux_alive_noc_p
ffff800081ecae50 d mout_cmu_cp_shared2_clk_p
ffff800081ecae70 d mout_cmu_cp_shared0_clk_p
ffff800081ecae90 d mout_cmu_cp_hispeedy_clk_p
ffff800081ecaea0 d mout_cmu_sdma_noc_p
ffff800081ecaee0 d mout_cmu_nocl1c_noc_p
ffff800081ecaf20 d mout_cmu_nocl1b_noc0_p
ffff800081ecaf60 d mout_cmu_nocl1a_noc_p
ffff800081ecafa0 d mout_cmu_nocl0_noc_p
ffff800081ecafe0 d mout_cmu_m2m_noc_p
ffff800081ecb020 d mout_cmu_ufs_mmc_card_p
ffff800081ecb040 d mout_cmu_gnpu_noc_p
ffff800081ecb080 d mout_cmu_g3d_switch_p
ffff800081ecb0c0 d mout_cmu_dsu_switch_p
ffff800081ecb100 d mout_cmu_dsp_noc_p
ffff800081ecb140 d mout_cmu_dpuf_noc_p
ffff800081ecb150 d mout_cmu_dpub_noc_p
ffff800081ecb160 d mout_cmu_dnc_noc_p
ffff800081ecb1a0 d mout_cmu_cpucl2_switch_p
ffff800081ecb1e0 d mout_cmu_cpucl1_switch_p
ffff800081ecb220 d mout_cmu_cpucl0_switch_p
ffff800081ecb260 d mout_cmu_cpucl0_dbg_noc_p
ffff800081ecb280 d mout_cmu_aud_cpu_p
ffff800081ecb2c0 d mout_cmu_aud_audif1_p
ffff800081ecb300 d mout_cmu_aud_audif0_p
ffff800081ecb340 d mout_cmu_cp_mpll_clk_user_parents
ffff800081ecb348 d mout_cmu_cp_mpll_clk_d2_user_parents
ffff800081ecb350 d top_clk_regs
ffff800081ecbe38 d aud_cmu_info
ffff800081ecbed8 d mscl_cmu_info
ffff800081ecbf78 d fsys1_cmu_info
ffff800081ecc018 d fsys0_cmu_info
ffff800081ecc0b8 d peris_cmu_info
ffff800081ecc158 d peric1_cmu_info
ffff800081ecc1f8 d peric0_cmu_info
ffff800081ecc298 d ccore_cmu_info
ffff800081ecc338 d top1_cmu_info
ffff800081ecc3d8 d top0_cmu_info
ffff800081ecc478 d topc_cmu_info
ffff800081ecc518 d aud_gate_clks
ffff800081ecc848 d aud_div_clks
ffff800081ecca08 d aud_mux_clks
ffff800081eccab0 d aud_clk_regs
ffff800081eccae0 d mout_aud_group_p
ffff800081eccaf0 d mout_aud_pll_user_p
ffff800081eccb00 d mscl_gate_clks
ffff800081ecd0a0 d mscl_div_clks
ffff800081ecd0d8 d mscl_mux_clks
ffff800081ecd110 d mscl_clk_regs
ffff800081ecd130 d mout_aclk_mscl_532_user_p
ffff800081ecd140 d fsys1_gate_clks
ffff800081ecd320 d fsys1_div_clks
ffff800081ecd358 d fsys1_mux_clks
ffff800081ecd550 d fsys1_clk_regs
ffff800081ecd598 d fixed_rate_clks_fsys1
ffff800081ecd610 d mout_phyclk_ufs20_rx1_user_p
ffff800081ecd620 d mout_phyclk_ufs20_rx0_user_p
ffff800081ecd630 d mout_phyclk_ufs20_tx0_user_p
ffff800081ecd640 d mout_sclk_ufsunipro20_user_p
ffff800081ecd650 d mout_sclk_mmc1_user_p
ffff800081ecd660 d mout_sclk_mmc0_user_p
ffff800081ecd670 d mout_fsys1_group_p
ffff800081ecd688 d mout_aclk_fsys1_200_user_p
ffff800081ecd698 d fsys0_gate_clks
ffff800081ecd878 d fsys0_mux_clks
ffff800081ecd990 d fsys0_clk_regs
ffff800081ecd9d0 d fixed_rate_clks_fsys0
ffff800081ecda20 d mout_phyclk_usbdrd300_udrd30_pipe_pclk_user_p
ffff800081ecda30 d mout_phyclk_usbdrd300_udrd30_phyclk_user_p
ffff800081ecda40 d mout_sclk_usbdrd300_user_p
ffff800081ecda50 d mout_sclk_mmc2_user_p
ffff800081ecda60 d mout_aclk_fsys0_200_user_p
ffff800081ecda70 d peris_gate_clks
ffff800081ecdb60 d peris_mux_clks
ffff800081ecdb98 d peris_clk_regs
ffff800081ecdbc0 d mout_aclk_peris_66_user_p
ffff800081ecdbd0 d peric1_gate_clks
ffff800081ece0e0 d peric1_mux_clks
ffff800081ece2d8 d peric1_clk_regs
ffff800081ece300 d mout_sclk_spi4_user_p
ffff800081ece310 d mout_sclk_spi3_user_p
ffff800081ece320 d mout_sclk_spi2_user_p
ffff800081ece330 d mout_sclk_spi1_user_p
ffff800081ece340 d mout_sclk_spi0_user_p
ffff800081ece350 d mout_sclk_uart3_user_p
ffff800081ece360 d mout_sclk_uart2_user_p
ffff800081ece370 d mout_sclk_uart1_user_p
ffff800081ece380 d mout_aclk_peric1_66_user_p
ffff800081ece390 d peric0_gate_clks
ffff800081ece5d0 d peric0_mux_clks
ffff800081ece640 d peric0_clk_regs
ffff800081ece658 d mout_sclk_uart0_user_p
ffff800081ece668 d mout_aclk_peric0_66_user_p
ffff800081ece678 d ccore_gate_clks
ffff800081ece6a8 d ccore_mux_clks
ffff800081ece6e0 d ccore_clk_regs
ffff800081ece6f0 d mout_aclk_ccore_133_user_p
ffff800081ece700 d top1_fixed_factor_clks
ffff800081ece7c0 d top1_gate_clks
ffff800081ece970 d top1_div_clks
ffff800081eceb68 d top1_mux_clks
ffff800081ecef58 d top1_clk_regs
ffff800081ecefc8 d mout_top1_group1
ffff800081ecefe8 d mout_top1_mfc_pll_half_p
ffff800081eceff8 d mout_top1_cc_pll_half_p
ffff800081ecf008 d mout_top1_bus1_pll_half_p
ffff800081ecf018 d mout_top1_bus0_pll_half_p
ffff800081ecf028 d mout_top1_mfc_pll_user_p
ffff800081ecf038 d mout_top1_cc_pll_user_p
ffff800081ecf048 d mout_top1_bus1_pll_user_p
ffff800081ecf058 d mout_top1_bus0_pll_user_p
ffff800081ecf068 d top0_fixed_factor_clks
ffff800081ecf128 d top0_gate_clks
ffff800081ecf3c8 d top0_div_clks
ffff800081ecf6d8 d top0_mux_clks
ffff800081ecfbe0 d top0_clk_regs
ffff800081ecfc60 d mout_top0_group4
ffff800081ecfc80 d mout_top0_group3
ffff800081ecfcb0 d mout_top0_group1
ffff800081ecfcd0 d mout_top0_mfc_pll_half_p
ffff800081ecfce0 d mout_top0_cc_pll_half_p
ffff800081ecfcf0 d mout_top0_bus1_pll_half_p
ffff800081ecfd00 d mout_top0_bus0_pll_half_p
ffff800081ecfd10 d mout_top0_aud_pll_user_p
ffff800081ecfd20 d mout_top0_mfc_pll_user_p
ffff800081ecfd30 d mout_top0_cc_pll_user_p
ffff800081ecfd40 d mout_top0_bus1_pll_user_p
ffff800081ecfd50 d mout_top0_bus0_pll_user_p
ffff800081ecfd60 d topc_pll_clks
ffff800081ecfe78 d topc_gate_clks
ffff800081ed00b8 d pll1460x_24mhz_tbl
ffff800081ed0100 d topc_div_clks
ffff800081ed02c0 d topc_mux_clks
ffff800081ed0598 d topc_clk_regs
ffff800081ed0620 d mout_topc_bus0_pll_out_p
ffff800081ed0630 d mout_topc_mfc_pll_half_p
ffff800081ed0640 d mout_topc_cc_pll_half_p
ffff800081ed0650 d mout_topc_bus1_pll_half_p
ffff800081ed0660 d mout_topc_bus0_pll_half_p
ffff800081ed0678 d mout_topc_group2
ffff800081ed0698 d mout_topc_mfc_pll_ctrl_p
ffff800081ed06a8 d mout_topc_cc_pll_ctrl_p
ffff800081ed06b8 d mout_topc_bus1_pll_ctrl_p
ffff800081ed06c8 d mout_topc_bus0_pll_ctrl_p
ffff800081ed06d8 d mout_topc_aud_pll_ctrl_p
ffff800081ed06e8 d topc_fixed_factor_clks
ffff800081ed07d8 d peri_cmu_info
ffff800081ed0878 d peri_gate_clks
ffff800081ed1148 d peri_clk_regs
ffff800081ed12c0 d mfcmscl_cmu_info
ffff800081ed1360 d mfcmscl_gate_clks
ffff800081ed1510 d mfcmscl_div_clks
ffff800081ed1548 d mfcmscl_mux_clks
ffff800081ed15b8 d mout_mfcmscl_mscl_user_p
ffff800081ed15c8 d mout_mfcmscl_mfc_user_p
ffff800081ed15d8 d mfcmscl_clk_regs
ffff800081ed1638 d isp_cmu_info
ffff800081ed16d8 d isp_gate_clks
ffff800081ed1a38 d isp_div_clks
ffff800081ed1aa8 d isp_mux_clks
ffff800081ed1c30 d mout_isp_vra_p
ffff800081ed1c40 d mout_isp_ispd_p
ffff800081ed1c50 d mout_isp_isp_p
ffff800081ed1c60 d mout_isp_cam_p
ffff800081ed1c70 d mout_isp_vra_user_p
ffff800081ed1c80 d mout_isp_user_p
ffff800081ed1c90 d mout_isp_cam_user_p
ffff800081ed1ca0 d isp_pll_clks
ffff800081ed1cd8 d isp_fixed_clks
ffff800081ed1d28 d isp_clk_regs
ffff800081ed1e10 d g3d_cmu_info
ffff800081ed1eb0 d g3d_gate_clks
ffff800081ed20f0 d g3d_div_clks
ffff800081ed2160 d g3d_mux_clks
ffff800081ed21d0 d mout_g3d_p
ffff800081ed21e0 d mout_g3d_switch_user_p
ffff800081ed21f0 d g3d_pll_clks
ffff800081ed2228 d g3d_clk_regs
ffff800081ed22b8 d fsys_cmu_info
ffff800081ed2358 d fsys_gate_clks
ffff800081ed2658 d fsys_pll_clks
ffff800081ed2690 d fsys_fixed_clks
ffff800081ed26b8 d fsys_clk_regs
ffff800081ed2748 d dispaud_cmu_info
ffff800081ed27e8 d dispaud_gate_clks
ffff800081ed2d58 d dispaud_div_clks
ffff800081ed2e70 d dispaud_mux_clks
ffff800081ed2fc0 d mout_dispaud_mi2s_p
ffff800081ed2fd0 d mout_dispaud_decon_vclk_p
ffff800081ed2fe0 d mout_dispaud_decon_eclk_p
ffff800081ed2ff0 d mout_dispaud_decon_vclk_user_p
ffff800081ed3000 d mout_dispaud_decon_eclk_user_p
ffff800081ed3010 d mout_dispaud_bus_user_p
ffff800081ed3020 d dispaud_pll_clks
ffff800081ed3090 d dispaud_fixed_clks
ffff800081ed31a8 d dispaud_clk_regs
ffff800081ed3308 d mif_cmu_info
ffff800081ed33a8 d mif_gate_clks
ffff800081ed40c8 d mif_div_clks
ffff800081ed4720 d mif_mux_clks
ffff800081ed4cd0 d mout_mif_busd_p
ffff800081ed4ce8 d mout_mif_cmu_peri_uart0_p
ffff800081ed4cf8 d mout_mif_cmu_peri_uart2_p
ffff800081ed4d08 d mout_mif_cmu_peri_uart1_p
ffff800081ed4d18 d mout_mif_cmu_peri_spi3_p
ffff800081ed4d28 d mout_mif_cmu_peri_spi4_p
ffff800081ed4d38 d mout_mif_cmu_peri_spi1_p
ffff800081ed4d48 d mout_mif_cmu_peri_spi2_p
ffff800081ed4d58 d mout_mif_cmu_peri_spi0_p
ffff800081ed4d68 d mout_mif_cmu_peri_bus_p
ffff800081ed4d78 d mout_mif_cmu_mfcmscl_mscl_p
ffff800081ed4d90 d mout_mif_cmu_mfcmscl_mfc_p
ffff800081ed4da8 d mout_mif_cmu_isp_vra_p
ffff800081ed4dc0 d mout_mif_cmu_isp_sensor2_p
ffff800081ed4dd0 d mout_mif_cmu_isp_sensor1_p
ffff800081ed4de0 d mout_mif_cmu_isp_sensor0_p
ffff800081ed4df0 d mout_mif_cmu_isp_isp_p
ffff800081ed4e00 d mout_mif_cmu_isp_cam_p
ffff800081ed4e10 d mout_mif_cmu_fsys_usb20drd_refclk_p
ffff800081ed4e20 d mout_mif_cmu_fsys_mmc2_p
ffff800081ed4e30 d mout_mif_cmu_fsys_mmc1_p
ffff800081ed4e40 d mout_mif_cmu_fsys_mmc0_p
ffff800081ed4e50 d mout_mif_cmu_fsys_bus_p
ffff800081ed4e60 d mout_mif_cmu_dispaud_decon_vclk_p
ffff800081ed4e70 d mout_mif_cmu_dispaud_decon_eclk_p
ffff800081ed4e80 d mout_mif_cmu_dispaud_bus_p
ffff800081ed4e90 d mif_pll_clks
ffff800081ed4f38 d mif_fixed_factor_clks
ffff800081ed4fc8 d mif_clk_regs
ffff800081ed53e0 d peri_cmu_info
ffff800081ed5480 d top_cmu_info
ffff800081ed5520 d fsys_cmu_info
ffff800081ed55c0 d fsys_gate_clks
ffff800081ed5800 d fsys_mux_clks
ffff800081ed5950 d mout_usb_pll_p
ffff800081ed5960 d mout_fsys_usb30drd_user_p
ffff800081ed5970 d mout_fsys_mmc_sdio_user_p
ffff800081ed5980 d mout_fsys_mmc_embd_user_p
ffff800081ed5990 d mout_fsys_mmc_card_user_p
ffff800081ed59a0 d mout_fsys_bus_user_p
ffff800081ed59b0 d fsys_pll_clks
ffff800081ed59e8 d pll_usb_rate_table
ffff800081ed5a10 d fsys_clk_regs
ffff800081ed5aa8 d core_cmu_info
ffff800081ed5b48 d core_gate_clks
ffff800081ed5cf8 d core_div_clks
ffff800081ed5d30 d core_mux_clks
ffff800081ed5e10 d mout_core_gic_p
ffff800081ed5e20 d mout_core_g3d_user_p
ffff800081ed5e30 d mout_core_cci_user_p
ffff800081ed5e40 d mout_core_bus_user_p
ffff800081ed5e50 d core_clk_regs
ffff800081ed5ec0 d peri_gate_clks
ffff800081ed6520 d peri_mux_clks
ffff800081ed6718 d mout_peri_usi2_user_p
ffff800081ed6728 d mout_peri_usi1_user_p
ffff800081ed6738 d mout_peri_usi0_user_p
ffff800081ed6748 d mout_peri_uart2_user_p
ffff800081ed6758 d mout_peri_uart1_user_p
ffff800081ed6768 d mout_peri_uart0_user_p
ffff800081ed6778 d mout_peri_spi1_user_p
ffff800081ed6788 d mout_peri_spi0_user_p
ffff800081ed6798 d mout_peri_bus_user_p
ffff800081ed67a8 d peri_clk_regs
ffff800081ed6900 d top_gate_clks
ffff800081ed6c30 d top_div_clks
ffff800081ed7170 d top_mux_clks
ffff800081ed7598 d mout_fsys_usb30drd_p
ffff800081ed75a8 d mout_fsys_mmc_sdio_p
ffff800081ed75b8 d mout_fsys_mmc_embd_p
ffff800081ed75c8 d mout_fsys_mmc_card_p
ffff800081ed75d8 d mout_fsys_bus_p
ffff800081ed75e8 d mout_peri_usi2_p
ffff800081ed75f8 d mout_peri_usi1_p
ffff800081ed7608 d mout_peri_usi0_p
ffff800081ed7618 d mout_peri_uart2_p
ffff800081ed7628 d mout_peri_uart1_p
ffff800081ed7638 d mout_peri_uart0_p
ffff800081ed7648 d mout_peri_spi1_p
ffff800081ed7658 d mout_peri_spi0_p
ffff800081ed7668 d mout_peri_bus_p
ffff800081ed7678 d mout_core_g3d_p
ffff800081ed7698 d mout_core_cci_p
ffff800081ed76b8 d mout_core_bus_p
ffff800081ed76d8 d mout_shared1_pll_p
ffff800081ed76e8 d mout_shared0_pll_p
ffff800081ed76f8 d top_pll_clks
ffff800081ed7768 d top_clk_regs
ffff800081ed7958 d peri_cmu_info
ffff800081ed79f8 d cpucl1_cmu_info
ffff800081ed7a98 d cpucl0_cmu_info
ffff800081ed7b38 d top_cmu_info
ffff800081ed7bd8 d dpu_cmu_info
ffff800081ed7c78 d dpu_gate_clks
ffff800081ed7df8 d dpu_div_clks
ffff800081ed7e30 d dpu_mux_clks
ffff800081ed7e68 d mout_dpu_user_p
ffff800081ed7e78 d dpu_clk_regs
ffff800081ed7ec8 d core_cmu_info
ffff800081ed7f68 d core_gate_clks
ffff800081ed8148 d core_div_clks
ffff800081ed8180 d core_mux_clks
ffff800081ed8298 d mout_core_gic_p
ffff800081ed82a8 d mout_core_sss_user_p
ffff800081ed82b8 d mout_core_mmc_embd_user_p
ffff800081ed82c8 d mout_core_cci_user_p
ffff800081ed82d8 d mout_core_bus_user_p
ffff800081ed82e8 d core_clk_regs
ffff800081ed8368 d peri_gate_clks
ffff800081ed8878 d peri_div_clks
ffff800081ed8958 d peri_mux_clks
ffff800081ed8a38 d mout_peri_spi_user_p
ffff800081ed8a48 d mout_peri_hsi2c_user_p
ffff800081ed8a58 d mout_peri_uart_user_p
ffff800081ed8a68 d mout_peri_bus_user_p
ffff800081ed8a78 d peri_clk_regs
ffff800081ed8b90 d mfcmscl_cmu_info
ffff800081ed8c30 d mfcmscl_gate_clks
ffff800081ed8e10 d mfcmscl_div_clks
ffff800081ed8e48 d mfcmscl_mux_clks
ffff800081ed8f28 d mout_mfcmscl_jpeg_user_p
ffff800081ed8f38 d mout_mfcmscl_mcsc_user_p
ffff800081ed8f48 d mout_mfcmscl_m2m_user_p
ffff800081ed8f58 d mout_mfcmscl_mfc_user_p
ffff800081ed8f68 d mfcmscl_clk_regs
ffff800081ed8fe0 d is_cmu_info
ffff800081ed9080 d is_gate_clks
ffff800081ed93e0 d is_div_clks
ffff800081ed9418 d is_mux_clks
ffff800081ed94f8 d mout_is_gdc_user_p
ffff800081ed9508 d mout_is_vra_user_p
ffff800081ed9518 d mout_is_itp_user_p
ffff800081ed9528 d mout_is_bus_user_p
ffff800081ed9538 d is_clk_regs
ffff800081ed95f0 d hsi_cmu_info
ffff800081ed9690 d hsi_gate_clks
ffff800081ed98d0 d hsi_mux_clks
ffff800081ed99b0 d mout_hsi_rtc_p
ffff800081ed99c0 d mout_hsi_usb20drd_user_p
ffff800081ed99d0 d mout_hsi_mmc_card_user_p
ffff800081ed99e0 d mout_hsi_bus_user_p
ffff800081ed99f0 d hsi_clk_regs
ffff800081ed9a70 d g3d_cmu_info
ffff800081ed9b10 d g3d_gate_clks
ffff800081ed9c60 d g3d_div_clks
ffff800081ed9c98 d g3d_mux_clks
ffff800081ed9d40 d g3d_pll_clks
ffff800081ed9d78 d mout_g3d_busd_p
ffff800081ed9d88 d mout_g3d_switch_user_p
ffff800081ed9d98 d mout_g3d_pll_p
ffff800081ed9da8 d g3d_clk_regs
ffff800081ed9e10 d cpucl1_cpu_clks
ffff800081ed9e40 d cpucl1_gate_clks
ffff800081ed9f60 d cpucl1_div_clks
ffff800081eda0e8 d cpucl1_mux_clks
ffff800081eda1c8 d cpucl1_pll_clks
ffff800081eda200 d mout_cpucl1_pll_p
ffff800081eda210 d mout_cpucl1_dbg_user_p
ffff800081eda220 d mout_cpucl1_switch_user_p
ffff800081eda230 d mout_pll_cpucl1_p
ffff800081eda240 d cpucl1_clk_regs
ffff800081eda2e0 d cpucl0_cpu_clks
ffff800081eda310 d exynos850_cluster_clk_d
ffff800081eda4f0 d cpucl0_gate_clks
ffff800081eda610 d cpucl0_div_clks
ffff800081eda798 d cpucl0_mux_clks
ffff800081eda878 d cpucl0_pll_clks
ffff800081eda8b0 d cpu_pll_rates
ffff800081edab60 d mout_cpucl0_pll_p
ffff800081edab70 d mout_cpucl0_dbg_user_p
ffff800081edab80 d mout_cpucl0_switch_user_p
ffff800081edab90 d mout_pll_cpucl0_p
ffff800081edaba0 d cpucl0_clk_regs
ffff800081edac40 d cmgp_cmu_info
ffff800081edace0 d cmgp_gate_clks
ffff800081edae60 d cmgp_div_clks
ffff800081edaf08 d cmgp_mux_clks
ffff800081edafb0 d cmgp_fixed_clks
ffff800081edafd8 d mout_cmgp_adc_p
ffff800081edafe8 d mout_cmgp_usi1_p
ffff800081edaff8 d mout_cmgp_usi0_p
ffff800081edb008 d cmgp_clk_regs
ffff800081edb078 d aud_cmu_info
ffff800081edb118 d aud_gate_clks
ffff800081edb538 d aud_div_clks
ffff800081edb8f0 d aud_mux_clks
ffff800081edbbc8 d aud_fixed_clks
ffff800081edbd08 d aud_pll_clks
ffff800081edbd40 d mout_aud_fm_p
ffff800081edbd50 d mout_aud_tick_usb_user_p
ffff800081edbd60 d mout_aud_uaif6_p
ffff800081edbd70 d mout_aud_uaif5_p
ffff800081edbd80 d mout_aud_uaif4_p
ffff800081edbd90 d mout_aud_uaif3_p
ffff800081edbda0 d mout_aud_uaif2_p
ffff800081edbdb0 d mout_aud_uaif1_p
ffff800081edbdc0 d mout_aud_uaif0_p
ffff800081edbdd0 d mout_aud_cpu_hch_p
ffff800081edbde0 d mout_aud_cpu_p
ffff800081edbdf0 d mout_aud_cpu_user_p
ffff800081edbe00 d mout_aud_pll_p
ffff800081edbe10 d aud_clk_regs
ffff800081edbfc0 d apm_cmu_info
ffff800081edc060 d apm_gate_clks
ffff800081edc240 d apm_div_clks
ffff800081edc2e8 d apm_mux_clks
ffff800081edc470 d apm_fixed_clks
ffff800081edc510 d mout_apm_i3c_p
ffff800081edc520 d mout_apm_bus_p
ffff800081edc540 d mout_clkcmu_chub_bus_p
ffff800081edc550 d mout_dll_user_p
ffff800081edc560 d mout_rco_apm_user_p
ffff800081edc570 d mout_rco_apm_i3c_user_p
ffff800081edc580 d mout_apm_bus_user_p
ffff800081edc590 d apm_clk_regs
ffff800081edc630 d top_gate_clks
ffff800081edcb10 d top_div_clks
ffff800081edd210 d top_mux_clks
ffff800081edd868 d mout_dpu_p
ffff800081edd888 d mout_peri_ip_p
ffff800081edd8a8 d mout_peri_uart_p
ffff800081edd8c8 d mout_peri_bus_p
ffff800081edd8d8 d mout_mfcmscl_jpeg_p
ffff800081edd8f8 d mout_mfcmscl_mcsc_p
ffff800081edd918 d mout_mfcmscl_m2m_p
ffff800081edd938 d mout_mfcmscl_mfc_p
ffff800081edd958 d mout_is_gdc_p
ffff800081edd978 d mout_is_vra_p
ffff800081edd998 d mout_is_itp_p
ffff800081edd9b8 d mout_is_bus_p
ffff800081edd9d8 d mout_hsi_usb20drd_p
ffff800081edd9f8 d mout_hsi_mmc_card_p
ffff800081edda38 d mout_hsi_bus_p
ffff800081edda48 d mout_g3d_switch_p
ffff800081edda68 d mout_cpucl1_dbg_p
ffff800081edda78 d mout_cpucl1_switch_p
ffff800081edda98 d mout_cpucl0_dbg_p
ffff800081eddaa8 d mout_cpucl0_switch_p
ffff800081eddac8 d mout_core_sss_p
ffff800081eddae8 d mout_core_mmc_embd_p
ffff800081eddb28 d mout_core_cci_p
ffff800081eddb48 d mout_core_bus_p
ffff800081eddb68 d mout_aud_p
ffff800081eddb88 d mout_clkcmu_apm_bus_p
ffff800081eddb98 d mout_mmc_pll_p
ffff800081eddba8 d mout_shared1_pll_p
ffff800081eddbb8 d mout_shared0_pll_p
ffff800081eddbc8 d top_pll_clks
ffff800081eddc70 d top_clk_regs
ffff800081eddf58 d peris_cmu_info
ffff800081eddff8 d top_cmu_info
ffff800081ede098 d peric1_cmu_info
ffff800081ede138 d peric1_gate_clks
ffff800081edea68 d peric1_mux_clks
ffff800081ededb0 d mout_peric1_usi13_user_p
ffff800081ededc0 d mout_peric1_usi12_user_p
ffff800081ededd0 d mout_peric1_usi11_user_p
ffff800081edede0 d mout_peric1_usi10_user_p
ffff800081ededf0 d mout_peric1_usi09_user_p
ffff800081edee00 d mout_peric1_usi08_user_p
ffff800081edee10 d mout_peric1_usi07_user_p
ffff800081edee20 d mout_peric1_usi06_user_p
ffff800081edee30 d mout_peric1_usi05_user_p
ffff800081edee40 d mout_peric1_usi04_user_p
ffff800081edee50 d mout_peric1_uart_bt_user_p
ffff800081edee60 d mout_peric1_spi_cam1_user_p
ffff800081edee70 d mout_peric1_spi_cam0_user_p
ffff800081edee80 d mout_peric1_speedy2_user_p
ffff800081edee90 d mout_peric1_bus_user_p
ffff800081edeea0 d peric1_clk_regs
ffff800081edf118 d peric0_cmu_info
ffff800081edf1b8 d peric0_gate_clks
ffff800081edf548 d peric0_mux_clks
ffff800081edf698 d mout_peric0_usi03_user_p
ffff800081edf6a8 d mout_peric0_usi02_user_p
ffff800081edf6b8 d mout_peric0_usi01_user_p
ffff800081edf6c8 d mout_peric0_usi00_user_p
ffff800081edf6d8 d mout_peric0_uart_dbg_user_p
ffff800081edf6e8 d mout_peric0_bus_user_p
ffff800081edf6f8 d peric0_clk_regs
ffff800081edf7f0 d fsys1_cmu_info
ffff800081edf890 d fsys1_gate_clks
ffff800081ee0010 d fsys1_mux_clks
ffff800081ee00f0 d mout_fsys1_ufs_card_user_p
ffff800081ee0100 d mout_fsys1_pcie_user_p
ffff800081ee0110 d mout_fsys1_mmc_card_user_p
ffff800081ee0120 d mout_fsys1_bus_user_p
ffff800081ee0130 d fsys1_clk_regs
ffff800081ee02b0 d fsys0_cmu_info
ffff800081ee0350 d fsys0_gate_clks
ffff800081ee0a10 d fsys0_mux_clks
ffff800081ee0b28 d mout_fsys0_usbdrd30_user_p
ffff800081ee0b38 d mout_fsys0_ufs_embd_user_p
ffff800081ee0b48 d mout_fsys0_mmc_embd_user_p
ffff800081ee0b58 d mout_fsys0_dpgtc_user_p
ffff800081ee0b68 d mout_fsys0_bus_user_p
ffff800081ee0b78 d fsys0_clk_regs
ffff800081ee0ce8 d peris_gate_clks
ffff800081ee1348 d peris_mux_clks
ffff800081ee13b8 d mout_peris_gic_p
ffff800081ee13c8 d mout_peris_bus_user_p
ffff800081ee13d8 d peris_clk_regs
ffff800081ee1500 d top_gate_clks
ffff800081ee21c0 d top_fixed_factor_clks
ffff800081ee23a0 d top_div_clks
ffff800081ee31d8 d top_mux_clks
ffff800081ee4160 d mout_cmu_vpu_bus_p
ffff800081ee4180 d mout_cmu_srdz_imgd_p
ffff800081ee41a0 d mout_cmu_srdz_bus_p
ffff800081ee41c0 d mout_cmu_peris_bus_p
ffff800081ee41d0 d mout_cmu_peric1_usi13_p
ffff800081ee41f0 d mout_cmu_peric1_usi12_p
ffff800081ee4210 d mout_cmu_peric1_usi11_p
ffff800081ee4230 d mout_cmu_peric1_usi10_p
ffff800081ee4250 d mout_cmu_peric1_usi09_p
ffff800081ee4270 d mout_cmu_peric1_usi08_p
ffff800081ee4290 d mout_cmu_peric1_usi07_p
ffff800081ee42b0 d mout_cmu_peric1_usi06_p
ffff800081ee42d0 d mout_cmu_peric1_usi05_p
ffff800081ee42f0 d mout_cmu_peric1_usi04_p
ffff800081ee4310 d mout_cmu_peric1_uart_bt_p
ffff800081ee4330 d mout_cmu_peric1_spi_cam1_p
ffff800081ee4350 d mout_cmu_peric1_spi_cam0_p
ffff800081ee4370 d mout_cmu_peric1_speedy2_p
ffff800081ee4390 d mout_cmu_peric1_bus_p
ffff800081ee43a0 d mout_cmu_peric0_usi03_p
ffff800081ee43c0 d mout_cmu_peric0_usi02_p
ffff800081ee43e0 d mout_cmu_peric0_usi01_p
ffff800081ee4400 d mout_cmu_peric0_usi00_p
ffff800081ee4420 d mout_cmu_peric0_uart_dbg_p
ffff800081ee4440 d mout_cmu_peric0_bus_p
ffff800081ee4450 d mout_cmu_mif_switch_p
ffff800081ee4490 d mout_cmu_mfc_bus_p
ffff800081ee44b0 d mout_cmu_iva_bus_p
ffff800081ee44d0 d mout_cmu_isplp_bus_p
ffff800081ee44f0 d mout_cmu_isphq_bus_p
ffff800081ee4510 d mout_cmu_imem_bus_p
ffff800081ee4530 d mout_cmu_hpm_p
ffff800081ee4550 d mout_cmu_g2d_jpeg_p
ffff800081ee4570 d mout_cmu_g2d_g2d_p
ffff800081ee4590 d mout_cmu_fsys1_ufs_card_p
ffff800081ee45b0 d mout_cmu_fsys1_pcie_p
ffff800081ee45c0 d mout_cmu_fsys1_mmc_card_p
ffff800081ee4600 d mout_cmu_fsys1_bus_p
ffff800081ee4610 d mout_fsys0_usbdrd30_p
ffff800081ee4630 d mout_fsys0_ufs_embd_p
ffff800081ee4650 d mout_fsys0_mmc_embd_p
ffff800081ee4690 d mout_fsys0_dpgtc_p
ffff800081ee46b0 d mout_fsys0_bus_p
ffff800081ee46d0 d mout_cmu_dsp_bus_p
ffff800081ee46f0 d mout_cmu_droopdetector_p
ffff800081ee4710 d mout_cmu_dpu_bus_p
ffff800081ee4750 d mout_cmu_dcam_imgd_p
ffff800081ee4770 d mout_cmu_dcam_bus_p
ffff800081ee4790 d mout_cmu_dbg_bus_p
ffff800081ee47b0 d mout_cmu_cpucl1_switch_p
ffff800081ee47d0 d mout_cmu_cpucl0_switch_p
ffff800081ee47f0 d mout_core_bus_p
ffff800081ee4830 d mout_cmu_cis_clk3_p
ffff800081ee4840 d mout_cmu_cis_clk2_p
ffff800081ee4850 d mout_cmu_cis_clk1_p
ffff800081ee4860 d mout_cmu_cis_clk0_p
ffff800081ee4870 d mout_cmu_cam_vra_p
ffff800081ee4890 d mout_cmu_cam_tpu1_p
ffff800081ee48b0 d mout_cmu_cam_tpu0_p
ffff800081ee48d0 d mout_cmu_cam_bus_p
ffff800081ee48f0 d mout_cmu_busc_busphsi2c_p
ffff800081ee4910 d mout_cmu_busc_bus_p
ffff800081ee4950 d mout_cmu_bus1_bus_p
ffff800081ee4970 d mout_cmu_apm_bus_p
ffff800081ee4980 d mout_cmu_abox_cpuabox_p
ffff800081ee49a0 d mout_cp2ap_mif_clk_user_p
ffff800081ee49a8 d mout_pll_shared4_p
ffff800081ee49b8 d mout_pll_shared3_p
ffff800081ee49c8 d mout_pll_shared2_p
ffff800081ee49d8 d mout_pll_shared1_p
ffff800081ee49e8 d mout_pll_shared0_p
ffff800081ee49f8 d top_pll_clks
ffff800081ee4b10 d pll_shared4_rate_table
ffff800081ee4b38 d pll_shared3_rate_table
ffff800081ee4b60 d pll_shared2_rate_table
ffff800081ee4b88 d pll_shared1_rate_table
ffff800081ee4bb0 d pll_shared0_rate_table
ffff800081ee4bd8 d top_clk_regs
ffff800081ee52d0 d peris_cmu_info
ffff800081ee5370 d top_cmu_info
ffff800081ee5410 d peris_gate_clks
ffff800081ee5740 d peris_mux_clks
ffff800081ee57b0 d mout_peris_clk_peris_gic_p
ffff800081ee57c0 d mout_peris_bus_user_p
ffff800081ee57d0 d peris_clk_regs
ffff800081ee58d8 d peric1_cmu_info
ffff800081ee5978 d peric1_gate_clks
ffff800081ee6608 d peric1_div_clks
ffff800081ee68a8 d peric1_mux_clks
ffff800081ee6b80 d mout_peric1_nonbususer_p
ffff800081ee6b90 d mout_peric1_bus_user_p
ffff800081ee6ba0 d peric1_clk_regs
ffff800081ee6ee8 d peric0_cmu_info
ffff800081ee6f88 d peric0_gate_clks
ffff800081ee7a38 d peric0_div_clks
ffff800081ee7ca0 d peric0_mux_clks
ffff800081ee7f40 d mout_peric0_nonbususer_p
ffff800081ee7f50 d mout_peric0_bus_user_p
ffff800081ee7f60 d peric0_clk_regs
ffff800081ee8240 d hsi0_cmu_info
ffff800081ee82e0 d hsi0_gate_clks
ffff800081ee8670 d hsi0_mux_clks
ffff800081ee8750 d mout_hsi0_dpgtc_user_p
ffff800081ee8760 d mout_hsi0_usbdp_debug_user_p
ffff800081ee8770 d mout_hsi0_usb31drd_user_p
ffff800081ee8780 d mout_hsi0_bus_user_p
ffff800081ee8790 d hsi0_clk_regs
ffff800081ee8848 d top_gate_clks
ffff800081ee92c8 d cmu_top_ffactor
ffff800081ee9388 d top_div_clks
ffff800081eea1f8 d top_mux_clks
ffff800081eeb0d8 d mout_cmu_clk_cmuref_p
ffff800081eeb0f8 d mout_cmu_cmuref_p
ffff800081eeb108 d mout_cmu_vra_bus_p
ffff800081eeb128 d mout_cmu_tnr_bus_p
ffff800081eeb168 d mout_cmu_ssp_bus_p
ffff800081eeb188 d mout_cmu_peris_bus_p
ffff800081eeb198 d mout_cmu_peric1_ip_p
ffff800081eeb1a8 d mout_cmu_peric1_bus_p
ffff800081eeb1b8 d mout_cmu_peric0_ip_p
ffff800081eeb1c8 d mout_cmu_peric0_bus_p
ffff800081eeb1d8 d mout_cmu_npu_bus_p
ffff800081eeb218 d mout_cmu_mif_switch_p
ffff800081eeb258 d mout_cmu_mif_busp_p
ffff800081eeb278 d mout_cmu_mfc0_wfd_p
ffff800081eeb298 d mout_cmu_mfc0_mfc0_p
ffff800081eeb2b8 d mout_cmu_cmu_boost_cpu_p
ffff800081eeb2d8 d mout_cmu_mcsc_gdc_p
ffff800081eeb318 d mout_cmu_mcsc_bus_p
ffff800081eeb358 d mout_cmu_itp_bus_p
ffff800081eeb398 d mout_cmu_ipp_bus_p
ffff800081eeb3d8 d mout_cmu_hsi2_pcie_p
ffff800081eeb3e8 d mout_cmu_hsi2_bus_p
ffff800081eeb3f8 d mout_cmu_hsi1_ufs_embd_p
ffff800081eeb418 d mout_cmu_hsi1_ufs_card_p
ffff800081eeb438 d mout_cmu_hsi1_pcie_p
ffff800081eeb448 d mout_cmu_hsi1_mmc_card_p
ffff800081eeb468 d mout_cmu_hsi1_bus_p
ffff800081eeb4a8 d mout_cmu_hsi0_usbdp_debug_p
ffff800081eeb4b8 d mout_cmu_hsi0_usb31drd_p
ffff800081eeb4d8 d mout_cmu_hsi0_dpgtc_p
ffff800081eeb4f8 d mout_cmu_hsi0_bus_p
ffff800081eeb508 d mout_cmu_hpm_p
ffff800081eeb528 d mout_cmu_g2d_mscl_p
ffff800081eeb548 d mout_cmu_g2d_g2d_p
ffff800081eeb568 d mout_cmu_dsp_bus_p
ffff800081eeb5a8 d mout_cmu_dpu_alt_p
ffff800081eeb5c8 d mout_cmu_dpu_p
ffff800081eeb5d8 d mout_cmu_dns_bus_p
ffff800081eeb618 d mout_cmu_dnc_busm_p
ffff800081eeb638 d mout_cmu_dnc_bus_p
ffff800081eeb658 d mout_cmu_csis_ois_mcu_p
ffff800081eeb668 d mout_cmu_csis_bus_p
ffff800081eeb688 d mout_cmu_cpucl2_switch_p
ffff800081eeb6a8 d mout_cmu_cpucl2_busp_p
ffff800081eeb6b8 d mout_cmu_cpucl1_switch_p
ffff800081eeb6d8 d mout_cmu_cpucl0_switch_p
ffff800081eeb6f8 d mout_cmu_cpucl0_dbg_bus_p
ffff800081eeb718 d mout_cmu_core_bus_p
ffff800081eeb758 d mout_cmu_cmu_boost_p
ffff800081eeb778 d mout_cmu_cis_clk5_p
ffff800081eeb788 d mout_cmu_cis_clk4_p
ffff800081eeb798 d mout_cmu_cis_clk3_p
ffff800081eeb7a8 d mout_cmu_cis_clk2_p
ffff800081eeb7b8 d mout_cmu_cis_clk1_p
ffff800081eeb7c8 d mout_cmu_cis_clk0_p
ffff800081eeb7d8 d mout_cmu_bus1_sss_p
ffff800081eeb7f8 d mout_cmu_bus1_bus_p
ffff800081eeb818 d mout_cmu_bus0_bus_p
ffff800081eeb838 d mout_cmu_aud_cpu_p
ffff800081eeb858 d mout_cmu_apm_bus_p
ffff800081eeb868 d mout_cmu_dpu_bus_p
ffff800081eeb878 d mout_pll_g3d_p
ffff800081eeb888 d mout_pll_mmc_p
ffff800081eeb898 d mout_pll_shared4_p
ffff800081eeb8a8 d mout_pll_shared3_p
ffff800081eeb8b8 d mout_pll_shared2_p
ffff800081eeb8c8 d mout_pll_shared1_p
ffff800081eeb8d8 d mout_pll_shared0_p
ffff800081eeb8e8 d top_pll_clks
ffff800081eeba70 d top_clk_regs
ffff800081eec100 d top_cmu_info
ffff800081eec1a0 d peris_cmu_info
ffff800081eec240 d peris_gate_clks
ffff800081eec2d0 d peris_mux_clks
ffff800081eec308 d mout_peris_bus_user_p
ffff800081eec318 d peris_clk_regs
ffff800081eec338 d peric1_cmu_info
ffff800081eec3d8 d peric1_gate_clks
ffff800081eec858 d peric1_div_clks
ffff800081eec9e0 d peric1_mux_clks
ffff800081eecbd8 d mout_peric1_usi_p
ffff800081eecbe8 d mout_peric1_ip_user_p
ffff800081eecbf8 d mout_peric1_bus_user_p
ffff800081eecc08 d peric1_clk_regs
ffff800081eecd48 d peric0_cmu_info
ffff800081eecde8 d peric0_gate_clks
ffff800081eed268 d peric0_div_clks
ffff800081eed3f0 d peric0_mux_clks
ffff800081eed5e8 d mout_peric0_usi_p
ffff800081eed5f8 d mout_peric0_ip_user_p
ffff800081eed608 d mout_peric0_bus_user_p
ffff800081eed618 d peric0_clk_regs
ffff800081eed758 d fsys2_cmu_info
ffff800081eed7f8 d fsys2_gate_clks
ffff800081eed8b8 d fsys2_mux_clks
ffff800081eed960 d mout_fsys2_ethernet_user_p
ffff800081eed970 d mout_fsys2_ufs_embd_user_p
ffff800081eed980 d mout_fsys2_bus_user_p
ffff800081eed990 d fsys2_clk_regs
ffff800081eed9c8 d fsys1_cmu_info
ffff800081eeda68 d fsys1_gate_clks
ffff800081eedc78 d fsys1_div_clks
ffff800081eedcb0 d fsys1_mux_clks
ffff800081eeddc8 d mout_fsys1_mmc_card_p
ffff800081eeddd8 d mout_fsys1_usbdrd_user_p
ffff800081eedde8 d mout_fsys1_mmc_card_user_p
ffff800081eeddf8 d mout_fsys1_mmc_pll_p
ffff800081eede08 d mout_fsys1_bus_user_p
ffff800081eede18 d fsys1_pll_clks
ffff800081eede50 d fsys1_clk_regs
ffff800081eede58 d fsys0_cmu_info
ffff800081eedef8 d fsys0_gate_clks
ffff800081eee4c8 d fsys0_mux_clks
ffff800081eee538 d mout_fsys0_pcie_user_p
ffff800081eee548 d mout_fsys0_bus_user_p
ffff800081eee558 d fsys0_clk_regs
ffff800081eee678 d dpum_cmu_info
ffff800081eee718 d dpum_gate_clks
ffff800081eee868 d dpum_div_clks
ffff800081eee8a0 d dpum_mux_clks
ffff800081eee8d8 d mout_dpum_bus_user_p
ffff800081eee8e8 d dpum_clk_regs
ffff800081eee930 d core_cmu_info
ffff800081eee9d0 d core_gate_clks
ffff800081eeea60 d core_div_clks
ffff800081eeea98 d core_mux_clks
ffff800081eeead0 d mout_core_bus_user_p
ffff800081eeeae0 d core_clk_regs
ffff800081eeeb10 d busmc_cmu_info
ffff800081eeebb0 d busmc_gate_clks
ffff800081eeec10 d busmc_div_clks
ffff800081eeec48 d busmc_mux_clks
ffff800081eeec80 d mout_busmc_bus_user_p
ffff800081eeec90 d busmc_clk_regs
ffff800081eeecb0 d top_gate_clks
ffff800081eef580 d top_fixed_factor_clks
ffff800081eef5b0 d top_div_clks
ffff800081ef0030 d top_mux_clks
ffff800081ef0a78 d mout_clkcmu_peric0_bus_p
ffff800081ef0a88 d mout_clkcmu_npu_bus_p
ffff800081ef0ac8 d mout_clkcmu_mif_switch_p
ffff800081ef0b08 d mout_clkcmu_g3d1_switch_p
ffff800081ef0b28 d mout_clkcmu_g3d0_switch_p
ffff800081ef0b48 d mout_clkcmu_g2d_g2d_p
ffff800081ef0b88 d mout_clkcmu_fsys2_ethernet_p
ffff800081ef0bb8 d mout_clkcmu_fsys1_mmc_card_p
ffff800081ef0bd8 d mout_clkcmu_fsys1_usbdrd_p
ffff800081ef0bf8 d mout_clkcmu_fsys1_bus_p
ffff800081ef0c18 d mout_clkcmu_fsys0_pcie_p
ffff800081ef0c28 d mout_clkcmu_fsys0_bus_p
ffff800081ef0c48 d mout_clkcmu_dpum_bus_p
ffff800081ef0c78 d mout_clkcmu_dptx_dpgtc_p
ffff800081ef0c98 d mout_clkcmu_dptx_bus_p
ffff800081ef0cb8 d mout_clkcmu_cpucl0_cluster_p
ffff800081ef0cf8 d mout_clkcmu_cpucl0_switch_p
ffff800081ef0d18 d mout_clkcmu_core_bus_p
ffff800081ef0d58 d mout_clkcmu_busc_bus_p
ffff800081ef0d78 d mout_clkcmu_aud_bus_p
ffff800081ef0d98 d mout_clkcmu_aud_cpu_p
ffff800081ef0dd0 d mout_clkcmu_apm_bus_p
ffff800081ef0df0 d mout_clkcmu_acc_bus_p
ffff800081ef0e10 d mout_clkcmu_cmu_cmuref_p
ffff800081ef0e20 d mout_clkcmu_cmu_boost_p
ffff800081ef0e40 d mout_shared4_pll_p
ffff800081ef0e50 d mout_shared3_pll_p
ffff800081ef0e60 d mout_shared2_pll_p
ffff800081ef0e70 d mout_shared1_pll_p
ffff800081ef0e80 d mout_shared0_pll_p
ffff800081ef0e90 d top_pll_clks
ffff800081ef0fa8 d top_clk_regs
ffff800081ef1470 d cpucl2_cmu_info
ffff800081ef1510 d cpucl1_cmu_info
ffff800081ef15b0 d cpucl0_cmu_info
ffff800081ef1650 d top_cmu_info
ffff800081ef16f0 d hsi2_cmu_info
ffff800081ef1790 d hsi2_div_clks
ffff800081ef1800 d hsi2_mux_clks
ffff800081ef18e0 d mout_clkcmu_hsi2_ethernet_user_p
ffff800081ef18f0 d mout_hsi2_ethernet_p
ffff800081ef1900 d mout_clkcmu_hsi2_ufs_embd_user_p
ffff800081ef1910 d mout_clkcmu_hsi2_noc_ufs_user_p
ffff800081ef1920 d hsi2_pll_clks
ffff800081ef1958 d hsi2_clk_regs
ffff800081ef1998 d hsi1_cmu_info
ffff800081ef1a38 d hsi1_mux_clks
ffff800081ef1b18 d mout_hsi1_usbdrd_p
ffff800081ef1b28 d mout_hsi1_usbdrd_user_p
ffff800081ef1b38 d mout_hsi1_noc_user_p
ffff800081ef1b48 d mout_hsi1_mmc_card_user_p
ffff800081ef1b58 d hsi1_clk_regs
ffff800081ef1b78 d hsi0_cmu_info
ffff800081ef1c18 d hsi0_div_clks
ffff800081ef1c50 d hsi0_mux_clks
ffff800081ef1c88 d mout_hsi0_noc_user_p
ffff800081ef1c98 d hsi0_clk_regs
ffff800081ef1ca8 d misc_cmu_info
ffff800081ef1d48 d misc_fixed_factor_clks
ffff800081ef1da8 d misc_div_clks
ffff800081ef1de0 d misc_mux_clks
ffff800081ef1e50 d mout_misc_gic_p
ffff800081ef1e60 d mout_misc_noc_user_p
ffff800081ef1e70 d misc_clk_regs
ffff800081ef1e98 d peric1_cmu_info
ffff800081ef1f38 d peric1_div_clks
ffff800081ef21a0 d peric1_mux_clks
ffff800081ef2478 d mout_peric1_usi_p
ffff800081ef2488 d mout_peric1_noc_user_p
ffff800081ef2498 d mout_peric1_ip_user_p
ffff800081ef24a8 d peric1_clk_regs
ffff800081ef2568 d peric0_cmu_info
ffff800081ef2608 d peric0_div_clks
ffff800081ef2870 d peric0_mux_clks
ffff800081ef2b48 d mout_peric0_usi_p
ffff800081ef2b58 d mout_peric0_noc_user_p
ffff800081ef2b68 d mout_peric0_ip_user_p
ffff800081ef2b78 d peric0_clk_regs
ffff800081ef2c38 d cpucl2_div_clks
ffff800081ef2d88 d cpucl2_mux_clks
ffff800081ef2ea0 d cpucl2_pll_clks
ffff800081ef2ed8 d mout_cpucl2_core_p
ffff800081ef2ef0 d mout_cpucl2_cluster_p
ffff800081ef2f08 d mout_cpucl2_switch_user_p
ffff800081ef2f18 d mout_cpucl2_cluster_user_p
ffff800081ef2f28 d mout_pll_cpucl2_p
ffff800081ef2f38 d cpucl2_clk_regs
ffff800081ef2fa8 d cpucl1_div_clks
ffff800081ef30f8 d cpucl1_mux_clks
ffff800081ef3210 d cpucl1_pll_clks
ffff800081ef3248 d mout_cpucl1_core_p
ffff800081ef3260 d mout_cpucl1_cluster_p
ffff800081ef3278 d mout_cpucl1_switch_user_p
ffff800081ef3288 d mout_cpucl1_cluster_user_p
ffff800081ef3298 d mout_pll_cpucl1_p
ffff800081ef32a8 d cpucl1_clk_regs
ffff800081ef3318 d cpucl0_div_clks
ffff800081ef34d8 d cpucl0_mux_clks
ffff800081ef3628 d cpucl0_pll_clks
ffff800081ef3660 d cpu_pll_rates
ffff800081ef37f0 d mout_cpucl0_core_p
ffff800081ef3808 d mout_cpucl0_cluster_p
ffff800081ef3820 d mout_cpucl0_switch_user_p
ffff800081ef3830 d mout_cpucl0_dbg_user_p
ffff800081ef3840 d mout_cpucl0_cluster_user_p
ffff800081ef3850 d mout_pll_cpucl0_p
ffff800081ef3860 d cpucl0_clk_regs
ffff800081ef38e8 d top_fixed_factor_clks
ffff800081ef3d98 d top_div_clks
ffff800081ef4930 d top_mux_clks
ffff800081ef56c0 d mout_clkcmu_taa_noc_p
ffff800081ef5700 d mout_clkcmu_ssp_noc_p
ffff800081ef5720 d mout_clkcmu_snw_noc_p
ffff800081ef5760 d mout_clkcmu_sdma_noc_p
ffff800081ef57a0 d mout_clkcmu_peric1_ip_p
ffff800081ef57b0 d mout_clkcmu_peric1_noc_p
ffff800081ef57c0 d mout_clkcmu_peric0_ip_p
ffff800081ef57d0 d mout_clkcmu_peric0_noc_p
ffff800081ef57e0 d mout_clkcmu_nocl2_noc_p
ffff800081ef5820 d mout_clkcmu_nocl1_noc_p
ffff800081ef5860 d mout_clkcmu_nocl0_noc_p
ffff800081ef58a0 d mout_clkcmu_misc_noc_p
ffff800081ef58c0 d mout_clkcmu_mif_nocp_p
ffff800081ef58e0 d mout_clkcmu_mif_switch_p
ffff800081ef5920 d mout_clkcmu_mfd_noc_p
ffff800081ef5960 d mout_clkcmu_mfc_wfd_p
ffff800081ef5980 d mout_clkcmu_mfc_mfc_p
ffff800081ef59a0 d mout_clkcmu_m2m_jpeg_p
ffff800081ef59c0 d mout_clkcmu_m2m_noc_p
ffff800081ef59e0 d mout_clkcmu_isp_noc_p
ffff800081ef5a20 d mout_clkcmu_hsi2_ethernet_p
ffff800081ef5a40 d mout_clkcmu_hsi2_ufs_embd_p
ffff800081ef5a60 d mout_clkcmu_hsi2_noc_ufs_p
ffff800081ef5a80 d mout_clkcmu_hsi2_noc_p
ffff800081ef5aa0 d mout_clkcmu_hsi1_mmc_card_p
ffff800081ef5ac0 d mout_clkcmu_hsi1_usbdrd_p
ffff800081ef5ae0 d mout_clkcmu_hsi1_noc_p
ffff800081ef5b00 d mout_clkcmu_hsi0_noc_p
ffff800081ef5b20 d mout_clkcmu_gnpu_noc_p
ffff800081ef5b60 d mout_clkcmu_g3d_nocp_p
ffff800081ef5b80 d mout_clkcmu_g3d_switch_p
ffff800081ef5ba0 d mout_clkcmu_dsp_noc_p
ffff800081ef5be0 d mout_clkcmu_dpuf_noc_p
ffff800081ef5c18 d mout_clkcmu_dpub_dsim_p
ffff800081ef5c28 d mout_clkcmu_dpub_noc_p
ffff800081ef5c60 d mout_clkcmu_dptx_dposc_p
ffff800081ef5c70 d mout_clkcmu_dptx_dpgtc_p
ffff800081ef5c90 d mout_clkcmu_dptx_noc_p
ffff800081ef5cb0 d mout_clkcmu_dnc_noc_p
ffff800081ef5cf0 d mout_clkcmu_cpucl2_cluster_p
ffff800081ef5d30 d mout_clkcmu_cpucl2_switch_p
ffff800081ef5d50 d mout_clkcmu_cpucl1_cluster_p
ffff800081ef5d90 d mout_clkcmu_cpucl1_switch_p
ffff800081ef5db0 d mout_clkcmu_cpucl0_dbg_p
ffff800081ef5dd0 d mout_clkcmu_cpucl0_cluster_p
ffff800081ef5e10 d mout_clkcmu_cpucl0_switch_p
ffff800081ef5e30 d mout_clkcmu_aud_noc_p
ffff800081ef5e50 d mout_clkcmu_aud_cpu_p
ffff800081ef5e90 d mout_clkcmu_apm_noc_p
ffff800081ef5eb0 d mout_clkcmu_acc_orb_p
ffff800081ef5ef0 d mout_clkcmu_acc_noc_p
ffff800081ef5f30 d mout_clkcmu_cmu_cmuref_p
ffff800081ef5f40 d mout_clkcmu_cmu_boost_p
ffff800081ef5f60 d mout_mmc_pll_p
ffff800081ef5f70 d mout_shared5_pll_p
ffff800081ef5f80 d mout_shared4_pll_p
ffff800081ef5f90 d mout_shared3_pll_p
ffff800081ef5fa0 d mout_shared2_pll_p
ffff800081ef5fb0 d mout_shared1_pll_p
ffff800081ef5fc0 d mout_shared0_pll_p
ffff800081ef5fd0 d top_pll_clks
ffff800081ef6158 d top_clk_regs
ffff800081ef65d8 d misc_cmu_info
ffff800081ef6678 d top_cmu_info
ffff800081ef6718 d peric1_cmu_info
ffff800081ef67b8 d peric1_gate_clks
ffff800081ef6d58 d peric1_div_clks
ffff800081ef6ee0 d peric1_mux_clks
ffff800081ef70a0 d mout_peric1_nonbususer_p
ffff800081ef70b0 d mout_peric1_bus_user_p
ffff800081ef70c0 d peric1_clk_regs
ffff800081ef7308 d peric0_cmu_info
ffff800081ef73a8 d peric0_gate_clks
ffff800081ef7df8 d peric0_div_clks
ffff800081ef8060 d peric0_mux_clks
ffff800081ef8300 d mout_peric0_usi_usi_user_p
ffff800081ef8310 d mout_peric0_usi0_uart_user_p
ffff800081ef8320 d mout_peric0_i3c_user_p
ffff800081ef8330 d mout_peric0_bus_user_p
ffff800081ef8340 d peric0_clk_regs
ffff800081ef8738 d misc_gate_clks
ffff800081ef9398 d misc_div_clks
ffff800081ef9408 d misc_mux_clks
ffff800081ef94b0 d mout_misc_gic_p
ffff800081ef94c0 d mout_misc_sss_user_p
ffff800081ef94d0 d mout_misc_bus_user_p
ffff800081ef94e0 d misc_clk_regs
ffff800081ef98d0 d hsi2_cmu_info
ffff800081ef9970 d hsi2_gate_clks
ffff800081efa3f0 d hsi2_mux_clks
ffff800081efa4d0 d mout_hsi2_ufs_embd_user_p
ffff800081efa4e0 d mout_hsi2_pcie_user_p
ffff800081efa4f0 d mout_hsi2_mmc_card_user_p
ffff800081efa500 d mout_hsi2_bus_user_p
ffff800081efa510 d cmu_hsi2_clk_regs
ffff800081efa850 d hsi0_cmu_info
ffff800081efa8f0 d hsi0_fixed_clks
ffff800081efa968 d hsi0_gate_clks
ffff800081efb0b8 d hsi0_div_clks
ffff800081efb0f0 d hsi0_mux_clks
ffff800081efb358 d cmu_hsi0_pll_clks
ffff800081efb390 d cmu_hsi0_usb_pll_rates
ffff800081efb3d8 d mout_hsi0_usb31drd_p
ffff800081efb3f8 d mout_hsi0_usb20_ref_p
ffff800081efb408 d mout_hsi0_bus_p
ffff800081efb418 d mout_hsi0_usbdpdbg_user_p
ffff800081efb428 d mout_hsi0_usb31drd_user_p
ffff800081efb438 d mout_hsi0_usb20_user_p
ffff800081efb448 d mout_hsi0_tcxo_user_p
ffff800081efb458 d mout_hsi0_dpgtc_user_p
ffff800081efb468 d mout_hsi0_bus_user_p
ffff800081efb478 d mout_hsi0_alt_user_p
ffff800081efb488 d mout_pll_usb_p
ffff800081efb498 d hsi0_clk_regs
ffff800081efb7a0 d apm_cmu_info
ffff800081efb840 d apm_gate_clks
ffff800081efc3e0 d apm_div_clks
ffff800081efc4c0 d apm_mux_clks
ffff800081efc530 d apm_fixed_clks
ffff800081efc5a8 d mout_apm_funcsrc_p
ffff800081efc5c0 d mout_apm_func_p
ffff800081efc5e0 d apm_clk_regs
ffff800081efc810 d cmu_top_gate_clks
ffff800081efd590 d cmu_top_ffactor
ffff800081efd5f0 d cmu_top_div_clks
ffff800081efe578 d cmu_top_mux_clks
ffff800081eff538 d mout_cmu_cmuref_p
ffff800081eff548 d mout_cmu_tpu_uart_p
ffff800081eff568 d mout_cmu_tpu_tpuctl_p
ffff800081eff5a8 d mout_cmu_tpu_tpu_p
ffff800081eff5e8 d mout_cmu_tpu_bus_p
ffff800081eff628 d mout_cmu_top_cmuref_p
ffff800081eff648 d mout_cmu_top_boost_option1_p
ffff800081eff658 d mout_cmu_tnr_bus_p
ffff800081eff698 d mout_cmu_peric1_ip_p
ffff800081eff6b8 d mout_cmu_peric1_bus_p
ffff800081eff6d8 d mout_cmu_peric0_ip_p
ffff800081eff6f8 d mout_cmu_peric0_bus_p
ffff800081eff718 d mout_cmu_pdp_vra_p
ffff800081eff758 d mout_cmu_pdp_bus_p
ffff800081eff798 d mout_cmu_misc_sss_p
ffff800081eff7b8 d mout_cmu_misc_bus_p
ffff800081eff7d8 d mout_cmu_mif_switch_p
ffff800081eff818 d mout_cmu_mif_busp_p
ffff800081eff838 d mout_cmu_mfc_mfc_p
ffff800081eff878 d mout_cmu_mcsc_mcsc_p
ffff800081eff8b8 d mout_cmu_mcsc_itsc_p
ffff800081eff8f8 d mout_cmu_itp_bus_p
ffff800081eff938 d mout_cmu_ipp_bus_p
ffff800081eff978 d mout_cmu_hsi2_ufs_embd_p
ffff800081eff998 d mout_cmu_hsi2_pcie0_p
ffff800081eff9a8 d mout_cmu_hsi2_mmc_card_p
ffff800081eff9c8 d mout_cmu_hsi2_bus_p
ffff800081effa08 d mout_cmu_hsi1_pcie_p
ffff800081effa18 d mout_cmu_hsi1_bus_p
ffff800081effa40 d mout_cmu_hsi0_usbdpdbg_p
ffff800081effa50 d mout_cmu_hsi0_usb31drd_p
ffff800081effa60 d mout_cmu_hsi0_dpgtc_p
ffff800081effa80 d mout_cmu_hsi0_bus_p
ffff800081effac0 d mout_cmu_hpm_p
ffff800081effae0 d mout_cmu_gdc_scsc_p
ffff800081effb20 d mout_cmu_gdc_gdc1_p
ffff800081effb60 d mout_cmu_gdc_gdc0_p
ffff800081effba0 d mout_cmu_g3d_switch_p
ffff800081effbe0 d mout_cmu_g3d_glb_p
ffff800081effc20 d mout_cmu_g3d_busd_p
ffff800081effc60 d mout_cmu_g3aa_g3aa_p
ffff800081effca0 d mout_cmu_g2d_mscl_p
ffff800081effce0 d mout_cmu_g2d_g2d_p
ffff800081effd20 d mout_cmu_eh_bus_p
ffff800081effd60 d mout_cmu_dpu_p
ffff800081effda0 d mout_cmu_dns_bus_p
ffff800081effde0 d mout_cmu_disp_bus_p
ffff800081effe20 d mout_cmu_csis_bus_p
ffff800081effe60 d mout_cmu_cpucl2_switch_p
ffff800081effea0 d mout_cmu_cpucl1_switch_p
ffff800081effee0 d mout_cmu_cpucl0_switch_p
ffff800081efff20 d mout_cmu_cpucl0_dbg_p
ffff800081efff60 d mout_cmu_core_bus_p
ffff800081efffa0 d mout_cmu_cmu_boost_option1_p
ffff800081efffb0 d mout_cmu_cmu_boost_p
ffff800081efffd0 d mout_cmu_cis_clk0_7_p
ffff800081f00010 d mout_cmu_bus2_bus_p
ffff800081f00050 d mout_cmu_bus1_bus_p
ffff800081f00090 d mout_cmu_bus0_bus_p
ffff800081f000d0 d mout_cmu_bo_bus_p
ffff800081f00110 d mout_pll_spare_p
ffff800081f00120 d mout_pll_shared3_p
ffff800081f00130 d mout_pll_shared2_p
ffff800081f00140 d mout_pll_shared1_p
ffff800081f00150 d mout_pll_shared0_p
ffff800081f00160 d cmu_top_pll_clks
ffff800081f00278 d cmu_top_clk_regs
ffff800081f00bb8 d pmc_match
ffff800081f00d48 d pmc_match
ffff800081f00ed8 d rockchip_grf_dt_match
ffff800081f01838 d rk3588_sysgrf
ffff800081f01848 d rk3588_defaults
ffff800081f01858 d rk3576_iocgrf
ffff800081f01868 d rk3576_defaults_ioc_grf
ffff800081f01878 d rk3576_sysgrf
ffff800081f01888 d rk3576_defaults_sys_grf
ffff800081f018a8 d rk3566_pipegrf
ffff800081f018b8 d rk3566_defaults
ffff800081f018e8 d rk3399_grf
ffff800081f018f8 d rk3399_defaults
ffff800081f01908 d rk3368_grf
ffff800081f01918 d rk3368_defaults
ffff800081f01928 d rk3328_grf
ffff800081f01938 d rk3328_defaults
ffff800081f01948 d rk3288_grf
ffff800081f01958 d rk3288_defaults
ffff800081f01978 d rk3228_grf
ffff800081f01988 d rk3228_defaults
ffff800081f01998 d rk3128_grf
ffff800081f019a8 d rk3128_defaults
ffff800081f019c8 d rk3036_grf
ffff800081f019d8 d rk3036_defaults
ffff800081f019e8 d sunxi_mbus_platforms
ffff800081f01a70 d car_match
ffff800081f01fe8 d apbmisc_match
ffff800081f02498 d gpu_process_speedos
ffff800081f024a8 d cpu_process_speedos
ffff800081f024b8 d soc_process_speedos
ffff800081f024c8 d __setup_str_pd_ignore_unused_setup
ffff800081f024d9 d __setup_str_regulator_ignore_unused_setup
ffff800081f024f8 d sunxi_early_reset_dt_ids
ffff800081f02688 d __setup_str_sysrq_always_enabled_setup
ffff800081f0269d d __setup_str_param_setup_earlycon_console_alias
ffff800081f026a5 d __setup_str_param_setup_earlycon
ffff800081f026b0 d compiletime_seed.9
ffff800081f026f0 d __setup_str_parse_trust_bootloader
ffff800081f02708 d __setup_str_parse_trust_cpu
ffff800081f02719 d __setup_str_iommu_dma_setup
ffff800081f02726 d __setup_str_iommu_set_def_domain_type
ffff800081f02738 d __setup_str_iommu_dma_forcedac_setup
ffff800081f02747 d __setup_str_fw_devlink_sync_state_setup
ffff800081f0275d d __setup_str_fw_devlink_strict_setup
ffff800081f0276f d __setup_str_fw_devlink_setup
ffff800081f0277a d __setup_str_save_async_options
ffff800081f0278e d __setup_str_deferred_probe_timeout_setup
ffff800081f027a6 d __setup_str_mount_param
ffff800081f027b6 d __setup_str_numa_parse_early_param
ffff800081f027bb d __setup_str_ramdisk_size
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ffff800081f20c2c d __initcall__kmod_clk_mt8186_wpe__765_52_clk_mt8186_wpe_drv_init6
ffff800081f20c30 d __initcall__kmod_clk_mt8188_apmixedsys__765_154_clk_mt8188_apmixed_drv_init6
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ffff800081f20c38 d __initcall__kmod_clk_mt8188_peri_ao__765_58_clk_mt8188_peri_ao_drv_init6
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ffff800081f20c40 d __initcall__kmod_clk_mt8188_adsp_audio26m__765_49_clk_mt8188_adsp_audio26m_drv_init6
ffff800081f20c44 d __initcall__kmod_clk_mt8188_cam__765_135_clk_mt8188_cam_drv_init6
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ffff80008213afd8 d __compound_literal.12
ffff80008213b058 d __compound_literal.11
ffff80008213b0d8 d __compound_literal.10
ffff80008213b158 d __compound_literal.9
ffff80008213b1d8 d __compound_literal.8
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ffff80008213bf50 d mt7981_net_wo0_uart_txd_0_pins
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ffff80008213c048 d mt7981_wm_jtag_1_funcs
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ffff80008213c0c0 d mt7981_jtag_pins
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ffff80008213c610 d mt7986_i2c_groups
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ffff80008213c698 d mt7986_wf_dbdc_pins
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ffff80008213c778 d mt7986_mdc_mdio_pins
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ffff80008213c8d8 d mt7986_uart1_3_cts_rts_pins
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ffff80008213c8e8 d mt7986_uart1_3_rx_tx_pins
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ffff80008213c918 d mt7986_spi0_wp_hold_pins
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ffff80008213c930 d mt7986_spi0_pins
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ffff80008213c950 d mt7986_uart2_0_rx_tx_funcs
ffff80008213c958 d mt7986_uart2_0_rx_tx_pins
ffff80008213c960 d mt7986_uart1_2_cts_rts_funcs
ffff80008213c968 d mt7986_uart1_2_cts_rts_pins
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ffff80008213c978 d mt7986_uart1_2_rx_tx_pins
ffff80008213c980 d mt7986_spi1_2_funcs
ffff80008213c990 d mt7986_spi1_2_pins
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ffff80008213c9b0 d mt7986_uart1_1_pins
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ffff80008213cad0 d mt7986_uart1_0_pins
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ffff80008213cae8 d mt7986_i2c_pins
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ffff80008213ccf0 d mt7988_tops_uart0_1_funcs
ffff80008213ccf8 d mt7988_tops_uart1_0_funcs
ffff80008213cd00 d mt7988_net_wo2_uart_txd_0_funcs
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ffff80008213cd18 d mt7988_uart2_1_funcs
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ffff80008213cd90 d mt7988_sdcard_funcs
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ffff80008213ce18 d mt7988_spi0_funcs
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ffff80008213ce30 d mt7988_watchdog_funcs
ffff80008213ce38 d mt7988_pmic_funcs
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ffff80008213ce50 d mt7988_pcie_wake_n2_0_funcs
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ffff80008213cea8 d mt7988_pcie_p2_phy_i2c_funcs
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ffff80008213cf00 d mt7988_2p5g_ext_mdio_funcs
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ffff80008213cf38 d mt7988_xfi_phy_pll_i2c3_funcs
ffff80008213cf40 d mt7988_u32_phy_i2c1_funcs
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ffff80008213cf90 d mt7988_xfi_pextp_phy0_i2c_funcs
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ffff80008213cfb8 d mt7988_xfi_phy1_i2c0_funcs
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ffff80008213d058 d mt7988_tops_jtag0_1_funcs
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ffff8000821954f8 D acpi_gbl_fc_decode
ffff800082195518 D acpi_gbl_sb_decode
ffff800082195538 D acpi_gbl_bpb_decode
ffff800082195578 D acpi_gbl_ed_decode
ffff800082195588 D acpi_gbl_dp_decode
ffff800082195598 D acpi_gbl_cpo_decode
ffff8000821955a8 D acpi_gbl_cph_decode
ffff8000821955b8 D acpi_gbl_wm_decode
ffff8000821955c8 D acpi_gbl_sm_decode
ffff8000821955d8 D acpi_gbl_am_decode
ffff8000821955e8 D acpi_gbl_sbt_decode
ffff800082195610 D acpi_gbl_ct_decode
ffff800082195620 D acpi_gbl_dts_decode
ffff800082195650 D acpi_gbl_ior_decode
ffff800082195670 D acpi_gbl_ppc_decode
ffff800082195690 D acpi_gbl_typ_decode
ffff8000821956b0 D acpi_gbl_ttp_decode
ffff8000821956c0 D acpi_gbl_trs_decode
ffff8000821956d0 D acpi_gbl_siz_decode
ffff8000821956f0 D acpi_gbl_shr_decode
ffff800082195710 D acpi_gbl_rw_decode
ffff800082195720 D acpi_gbl_rng_decode
ffff800082195740 D acpi_gbl_phy_decode
ffff800082195760 D acpi_gbl_mtp_decode
ffff800082195780 D acpi_gbl_min_decode
ffff800082195790 D acpi_gbl_mem_decode
ffff8000821957b0 D acpi_gbl_max_decode
ffff8000821957c0 D acpi_gbl_ll_decode
ffff8000821957e0 D acpi_gbl_io_decode
ffff8000821957f0 D acpi_gbl_he_decode
ffff800082195800 D acpi_gbl_dec_decode
ffff800082195810 D acpi_gbl_consume_decode
ffff800082195820 D acpi_gbl_config_decode
ffff800082195840 D acpi_gbl_bm_decode
ffff800082195850 d pci_mcfg_list
ffff800082195860 d mcfg_quirks
ffff800082199d20 d acpi_ac_driver
ffff800082199de8 d slot_list
ffff800082199df8 d slot_list_lock
ffff800082199e18 d container_handler
ffff800082199eb8 d empty_nhlt
ffff800082199ee0 d pxm_to_node_map
ffff80008219a6e0 d node_to_pxm_map
ffff80008219aee0 d memory_device_handler
ffff80008219af80 d cache_time
ffff80008219af88 d acpi_battery_driver
ffff80008219b0e0 d acpi_battery_list
ffff80008219b0f0 d hook_mutex
ffff80008219b110 d battery_hook_list
ffff80008219b120 d acpi_battery_groups
ffff80008219b130 d acpi_battery_attrs
ffff80008219b140 d alarm_attr
ffff80008219b160 d acpi_hed_notify_list
ffff80008219b190 d acpi_hed_driver
ffff80008219b2e8 d whea_uuid_str.0
ffff80008219b310 d apei_resources_all
ffff80008219b330 d erst_ins_type
ffff80008219b460 d erst_record_id_cache
ffff80008219b498 d erst_info
ffff80008219b520 d cxl_cper_prot_err_fifo
ffff80008219bbb8 d ghes_devs
ffff80008219bbc8 d vendor_record_notify_list
ffff80008219bbf8 d _rs.20
ffff80008219bc18 d _rs.18
ffff80008219bc38 d _rs.16
ffff80008219bc58 d _rs.15
ffff80008219bc78 d _rs.8
ffff80008219bc98 d _rs.6
ffff80008219bcb8 d ghes_list_mutex
ffff80008219bcd8 d ghes_hed
ffff80008219bce8 d ghes_notifier_hed
ffff80008219bd00 d ghes_devs_mutex
ffff80008219bd20 d _rs.4
ffff80008219bd40 d ratelimit_corrected.11
ffff80008219bd60 d ratelimit_uncorrected.10
ffff80008219bd80 d _rs.14
ffff80008219bda0 d ghes_sea
ffff80008219bdb0 d ghes_platform_driver
ffff80008219be78 D cxl_cper_fifo
ffff80008219d110 d int340x_thermal_handler
ffff80008219d1b0 d iort_fwnode_list
ffff80008219d1c0 d iort_msi_chip_list
ffff80008219d1d0 d amba_handler
ffff80008219d270 d viot_pci_ranges
ffff80008219d280 d viot_iommus
ffff80008219d290 d viot_mmio_endpoints
ffff80008219d2a0 D pnp_lock
ffff80008219d2c0 d pnp_protocols
ffff80008219d2d0 D pnp_global
ffff80008219d2e0 d pnp_card_drivers
ffff80008219d2f0 D pnp_cards
ffff80008219d300 d dev_attr_name
ffff80008219d320 d dev_attr_card_id
ffff80008219d340 d pnp_reserve_irq
ffff80008219d380 d pnp_reserve_dma
ffff80008219d3a0 d pnp_reserve_io
ffff80008219d3e0 d pnp_reserve_mem
ffff80008219d420 D pnp_res_mutex
ffff80008219d440 D pnp_dev_groups
ffff80008219d450 d pnp_dev_attrs
ffff80008219d470 d dev_attr_id
ffff80008219d490 d dev_attr_resources
ffff80008219d4b0 d dev_attr_options
ffff80008219d4d0 d pnp_fixups
ffff80008219d5f0 d system_pnp_driver
ffff80008219d6c0 D pnpacpi_protocol
ffff80008219da48 d hp_ccsr_uuid
ffff80008219da60 d amba_proxy_drv
ffff80008219db18 d amba_dev_groups
ffff80008219db28 d amba_dev_attrs
ffff80008219db40 d dev_attr_resource
ffff80008219db60 d dev_attr_id
ffff80008219db80 d tegra_ahb_driver
ffff80008219dc48 d clocks_mutex
ffff80008219dc68 d clocks
ffff80008219dc78 d prepare_lock
ffff80008219dc98 d clk_notifier_list
ffff80008219dca8 d clk_rpm_list_lock
ffff80008219dcc8 d of_clk_mutex
ffff80008219dce8 d of_clk_providers
ffff80008219dcf8 d all_lists
ffff80008219dd10 d orphan_list
ffff80008219dd20 d clk_debug_lock
ffff80008219dd40 d print_fmt_clk_rate_request
ffff80008219ddd8 d print_fmt_clk_duty_cycle
ffff80008219de28 d print_fmt_clk_phase
ffff80008219de58 d print_fmt_clk_parent
ffff80008219de88 d print_fmt_clk_rate_range
ffff80008219dee0 d print_fmt_clk_rate
ffff80008219df18 d print_fmt_clk
ffff80008219df30 d trace_event_fields_clk_rate_request
ffff80008219e020 d trace_event_fields_clk_duty_cycle
ffff80008219e0c0 d trace_event_fields_clk_phase
ffff80008219e138 d trace_event_fields_clk_parent
ffff80008219e1b0 d trace_event_fields_clk_rate_range
ffff80008219e250 d trace_event_fields_clk_rate
ffff80008219e2c8 d trace_event_fields_clk
ffff80008219e318 d trace_event_type_funcs_clk_rate_request
ffff80008219e338 d trace_event_type_funcs_clk_duty_cycle
ffff80008219e358 d trace_event_type_funcs_clk_phase
ffff80008219e378 d trace_event_type_funcs_clk_parent
ffff80008219e398 d trace_event_type_funcs_clk_rate_range
ffff80008219e3b8 d trace_event_type_funcs_clk_rate
ffff80008219e3d8 d trace_event_type_funcs_clk
ffff80008219e3f8 d event_clk_rate_request_done
ffff80008219e470 d event_clk_rate_request_start
ffff80008219e4e8 d event_clk_set_duty_cycle_complete
ffff80008219e560 d event_clk_set_duty_cycle
ffff80008219e5d8 d event_clk_set_phase_complete
ffff80008219e650 d event_clk_set_phase
ffff80008219e6c8 d event_clk_set_parent_complete
ffff80008219e740 d event_clk_set_parent
ffff80008219e7b8 d event_clk_set_rate_range
ffff80008219e830 d event_clk_set_max_rate
ffff80008219e8a8 d event_clk_set_min_rate
ffff80008219e920 d event_clk_set_rate_complete
ffff80008219e998 d event_clk_set_rate
ffff80008219ea10 d event_clk_unprepare_complete
ffff80008219ea88 d event_clk_unprepare
ffff80008219eb00 d event_clk_prepare_complete
ffff80008219eb78 d event_clk_prepare
ffff80008219ebf0 d event_clk_disable_complete
ffff80008219ec68 d event_clk_disable
ffff80008219ece0 d event_clk_enable_complete
ffff80008219ed58 d event_clk_enable
ffff80008219edd0 D __SCK__tp_func_clk_rate_request_done
ffff80008219edd8 D __SCK__tp_func_clk_rate_request_start
ffff80008219ede0 D __SCK__tp_func_clk_set_duty_cycle_complete
ffff80008219ede8 D __SCK__tp_func_clk_set_duty_cycle
ffff80008219edf0 D __SCK__tp_func_clk_set_phase_complete
ffff80008219edf8 D __SCK__tp_func_clk_set_phase
ffff80008219ee00 D __SCK__tp_func_clk_set_parent_complete
ffff80008219ee08 D __SCK__tp_func_clk_set_parent
ffff80008219ee10 D __SCK__tp_func_clk_set_rate_range
ffff80008219ee18 D __SCK__tp_func_clk_set_max_rate
ffff80008219ee20 D __SCK__tp_func_clk_set_min_rate
ffff80008219ee28 D __SCK__tp_func_clk_set_rate_complete
ffff80008219ee30 D __SCK__tp_func_clk_set_rate
ffff80008219ee38 D __SCK__tp_func_clk_unprepare_complete
ffff80008219ee40 D __SCK__tp_func_clk_unprepare
ffff80008219ee48 D __SCK__tp_func_clk_prepare_complete
ffff80008219ee50 D __SCK__tp_func_clk_prepare
ffff80008219ee58 D __SCK__tp_func_clk_disable_complete
ffff80008219ee60 D __SCK__tp_func_clk_disable
ffff80008219ee68 D __SCK__tp_func_clk_enable_complete
ffff80008219ee70 D __SCK__tp_func_clk_enable
ffff80008219ee78 d of_fixed_factor_clk_driver
ffff80008219ef40 d of_fixed_clk_driver
ffff80008219f008 d gpio_clk_driver
ffff80008219f0d0 d gated_fixed_clk_driver
ffff80008219f198 d scmi_clocks_driver
ffff80008219f248 d clk_dvp_driver
ffff80008219f310 d bcm2835_clk_driver
ffff80008219f3d8 d __compound_literal.51
ffff80008219f3f0 d __compound_literal.50
ffff80008219f428 d __compound_literal.49
ffff80008219f460 d __compound_literal.48
ffff80008219f498 d __compound_literal.47
ffff80008219f4d0 d __compound_literal.46
ffff80008219f508 d __compound_literal.45
ffff80008219f540 d __compound_literal.44
ffff80008219f578 d __compound_literal.43
ffff80008219f5b0 d __compound_literal.42
ffff80008219f5e8 d __compound_literal.41
ffff80008219f620 d __compound_literal.40
ffff80008219f658 d __compound_literal.39
ffff80008219f690 d __compound_literal.38
ffff80008219f6c8 d __compound_literal.37
ffff80008219f700 d __compound_literal.36
ffff80008219f738 d __compound_literal.35
ffff80008219f770 d __compound_literal.34
ffff80008219f7a8 d __compound_literal.33
ffff80008219f7e0 d __compound_literal.32
ffff80008219f818 d __compound_literal.31
ffff80008219f850 d __compound_literal.30
ffff80008219f888 d __compound_literal.29
ffff80008219f8c0 d __compound_literal.28
ffff80008219f8f8 d __compound_literal.27
ffff80008219f930 d __compound_literal.26
ffff80008219f968 d __compound_literal.25
ffff80008219f9a0 d __compound_literal.24
ffff80008219f9d8 d __compound_literal.23
ffff80008219fa10 d __compound_literal.22
ffff80008219fa48 d __compound_literal.21
ffff80008219fa80 d __compound_literal.20
ffff80008219faa8 d __compound_literal.19
ffff80008219fad0 d __compound_literal.18
ffff80008219faf8 d __compound_literal.17
ffff80008219fb40 d __compound_literal.16
ffff80008219fb68 d __compound_literal.15
ffff80008219fb90 d __compound_literal.14
ffff80008219fbb8 d __compound_literal.13
ffff80008219fbe0 d __compound_literal.12
ffff80008219fc28 d __compound_literal.11
ffff80008219fc50 d __compound_literal.10
ffff80008219fc78 d __compound_literal.9
ffff80008219fca0 d __compound_literal.8
ffff80008219fcc8 d __compound_literal.7
ffff80008219fd10 d __compound_literal.6
ffff80008219fd38 d __compound_literal.5
ffff80008219fd80 d __compound_literal.4
ffff80008219fda8 d __compound_literal.3
ffff80008219fdd0 d __compound_literal.2
ffff80008219fdf8 d __compound_literal.1
ffff80008219fe20 d __compound_literal.0
ffff80008219fe68 d bcm2835_aux_clk_driver
ffff80008219ff30 d hi3516cv300_crg_driver
ffff80008219fff8 d wdt_mux_table
ffff8000821a0000 d pwm_mux_table
ffff8000821a0010 d mmc2_mux_table
ffff8000821a0018 d fmc_mux_table
ffff8000821a0030 d uart_mux_table
ffff8000821a0038 d hi3559av100_crg_driver
ffff8000821a0100 d hi3559av100_gate_clks
ffff8000821a0950 d hi3559av100_mux_clks_crg
ffff8000821a0bd8 d hi3559av100_shub_gate_clks
ffff8000821a0e40 d hi3559av100_shub_div_clks
ffff8000821a0ec0 d hi3559av100_shub_mux_clks
ffff8000821a0f50 d hi3559av100_shub_fixed_rate_clks
ffff8000821a1158 d hi3559av100_pll_clks
ffff8000821a11b8 d shub_uart_div_clk_table
ffff8000821a11d0 d shub_spi_clk_table
ffff8000821a11f0 d shub_uart_source_clk_mux_p
ffff8000821a1210 d shub_uart_source_clk_mux_table
ffff8000821a1220 d shub_source_clk_mux_p
ffff8000821a1240 d shub_source_clk_mux_table
ffff8000821a1250 d a73_clksel_mux_p
ffff8000821a1268 d uart_mux_p
ffff8000821a1280 d sysbus_mux_p
ffff8000821a1290 d sysapb_mux_p
ffff8000821a12a0 d mmc_mux_p
ffff8000821a12e0 d fmc_mux_p
ffff8000821a1320 d hi3660_clk_driver
ffff8000821a13e8 d hi3670_clk_driver
ffff8000821a14b0 d hi3798cv200_crg_driver
ffff8000821a1578 d hi3798cv200_phase_clks
ffff8000821a1608 d hi3798cv200_mux_clks
ffff8000821a1728 d mmc_phase_degrees
ffff8000821a1748 d mmc_phase_regvals
ffff8000821a1768 d sdio_mux_table
ffff8000821a1778 d comphy_mux_table
ffff8000821a1780 d mmc_mux_table
ffff8000821a1798 d hi3660_stub_clk_driver
ffff8000821a1860 d hi3660_stub_clks
ffff8000821a1980 d __compound_literal.3
ffff8000821a19b8 d __compound_literal.2
ffff8000821a19f0 d __compound_literal.1
ffff8000821a1a28 d __compound_literal.0
ffff8000821a1a60 d clk_mt6765_drv
ffff8000821a1b28 d top_aud_divs
ffff8000821a1cb0 d clk_mt6779_drv
ffff8000821a1d78 d clk_mt6779_infra_drv
ffff8000821a1e40 d clk_mt6795_apmixed_drv
ffff8000821a1f08 d pllfhs
ffff8000821a21c8 d clk_mt6795_infracfg_drv
ffff8000821a2290 d infra_ao_idx_map
ffff8000821a22a0 d infra_ao_rst_ofs
ffff8000821a22a8 d clk_mt6795_pericfg_drv
ffff8000821a2370 d peri_idx_map
ffff8000821a2378 d clk_mt6795_topckgen_drv
ffff8000821a2440 d top_aud_divs
ffff8000821a27f8 d clk_mt6795_mfg_drv
ffff8000821a28c0 d clk_mt6795_mm_drv
ffff8000821a2988 d clk_mt6795_vdecsys_drv
ffff8000821a2a50 d clk_mt6795_vencsys_drv
ffff8000821a2b18 d clk_mt6797_drv
ffff8000821a2be0 d clk_mt7981_apmixed_drv
ffff8000821a2ca8 d clk_mt7981_topckgen_drv
ffff8000821a2d70 d top_aud_divs
ffff8000821a2da8 d clk_mt7981_infracfg_drv
ffff8000821a2e70 d clk_mt7981_eth_drv
ffff8000821a2f38 d clk_mt7986_apmixed_drv
ffff8000821a3000 d clk_mt7986_topckgen_drv
ffff8000821a30c8 d clk_mt7986_infracfg_drv
ffff8000821a3190 d clk_mt7986_eth_drv
ffff8000821a3258 d clk_mt7988_apmixed_drv
ffff8000821a3320 d clk_mt7988_topckgen_drv
ffff8000821a33e8 d mcu_muxes
ffff8000821a3458 d clk_mt7988_infracfg_drv
ffff8000821a3520 d infra_rst_desc
ffff8000821a3548 d infra_idx_map
ffff8000821a3550 d infra_rst_ofs
ffff8000821a3558 d clk_mt7988_eth_drv
ffff8000821a3620 d ethwarp_idx_map
ffff8000821a3628 d ethwarp_rst_ofs
ffff8000821a3630 d clk_mt7988_xfipll_drv
ffff8000821a36f8 d clk_mt8167_apmixed_drv
ffff8000821a37c0 d clk_mt8167_drv
ffff8000821a3888 d clk_mt8167_audsys_drv
ffff8000821a3950 d clk_mt8167_imgsys_drv
ffff8000821a3a18 d clk_mt8167_mfgcfg_drv
ffff8000821a3ae0 d clk_mt8167_mm_drv
ffff8000821a3ba8 d clk_mt8167_vdec_drv
ffff8000821a3c70 d clk_mt8183_apmixed_drv
ffff8000821a3d38 d clk_mt8183_drv
ffff8000821a3e00 d infra_rst_ofs
ffff8000821a3e08 d top_aud_comp
ffff8000821a40a8 d mcu_muxes
ffff8000821a4150 d clk_mt8186_apmixed_drv
ffff8000821a4218 d pllfhs
ffff8000821a45e0 d clk_mt8186_topck_drv
ffff8000821a46a8 d top_muxes
ffff8000821a48d8 d clk_mt8186_infra_ao_drv
ffff8000821a49a0 d infra_ao_rst_desc
ffff8000821a49c8 d infra_ao_idx_map
ffff8000821a49d0 d infra_ao_rst_ofs
ffff8000821a49e0 d clk_mt8186_cam_drv
ffff8000821a4aa8 d clk_mt8186_img_drv
ffff8000821a4b70 d clk_mt8186_imp_iic_wrap_drv
ffff8000821a4c38 d clk_mt8186_ipe_drv
ffff8000821a4d00 d clk_mt8186_mcu_drv
ffff8000821a4dc8 d mcu_muxes
ffff8000821a4e70 d clk_mt8186_mdp_drv
ffff8000821a4f38 d clk_mt8186_mfg_drv
ffff8000821a5000 d clk_mt8186_mm_drv
ffff8000821a50c8 d clk_mt8186_vdec_drv
ffff8000821a5190 d clk_mt8186_venc_drv
ffff8000821a5258 d clk_mt8186_wpe_drv
ffff8000821a5320 d clk_mt8188_apmixed_drv
ffff8000821a53e8 d clk_mt8188_topck_drv
ffff8000821a54b0 d clk_mt8188_peri_ao_drv
ffff8000821a5578 d clk_mt8188_infra_ao_drv
ffff8000821a5640 d infra_ao_idx_map
ffff8000821a5648 d infra_ao_rst_ofs
ffff8000821a5658 d clk_mt8188_adsp_audio26m_drv
ffff8000821a5720 d clk_mt8188_cam_drv
ffff8000821a57e8 d cam_sys_rst_ofs
ffff8000821a57f0 d clk_mt8188_ccu_drv
ffff8000821a58b8 d clk_mt8188_imgsys_main_drv
ffff8000821a5980 d img_sys_rst_ofs
ffff8000821a5988 d clk_mt8188_imp_iic_wrap_drv
ffff8000821a5a50 d clk_mt8188_ipe_drv
ffff8000821a5b18 d ipe_sys_rst_ofs
ffff8000821a5b20 d clk_mt8188_mfgcfg_drv
ffff8000821a5be8 d clk_mt8188_vdec_drv
ffff8000821a5cb0 d clk_mt8188_vdo0_drv
ffff8000821a5d78 d clk_mt8188_vdo1_drv
ffff8000821a5e40 d clk_mt8188_venc1_drv
ffff8000821a5f08 d clk_mt8188_vpp0_drv
ffff8000821a5fd0 d clk_mt8188_vpp1_drv
ffff8000821a6098 d clk_mt8188_wpe_drv
ffff8000821a6160 d clk_mt8192_apmixed_drv
ffff8000821a6228 d pllfhs
ffff8000821a6438 d clk_mt8192_drv
ffff8000821a6500 d infra_ao_idx_map
ffff8000821a6510 d infra_ao_rst_ofs
ffff8000821a6520 d top_muxes
ffff8000821a69b8 d clk_mt8192_aud_drv
ffff8000821a6a80 d clk_mt8192_cam_drv
ffff8000821a6b48 d clk_mt8192_img_drv
ffff8000821a6c10 d clk_mt8192_imp_iic_wrap_drv
ffff8000821a6cd8 d clk_mt8192_ipe_drv
ffff8000821a6da0 d clk_mt8192_mdp_drv
ffff8000821a6e68 d clk_mt8192_mfg_drv
ffff8000821a6f30 d clk_mt8192_mm_drv
ffff8000821a6ff8 d clk_mt8192_msdc_drv
ffff8000821a70c0 d clk_mt8192_scp_adsp_drv
ffff8000821a7188 d clk_mt8192_vdec_drv
ffff8000821a7250 d clk_mt8192_venc_drv
ffff8000821a7318 d clk_mt8195_apmixed_drv
ffff8000821a73e0 d pllfhs
ffff8000821a7750 d clk_mt8195_topck_drv
ffff8000821a7818 d clk_mt8195_peri_ao_drv
ffff8000821a78e0 d clk_mt8195_infra_ao_drv
ffff8000821a79a8 d infra_ao_rst_desc
ffff8000821a79d0 d infra_ao_idx_map
ffff8000821a79e0 d infra_ao_rst_ofs
ffff8000821a79f0 d clk_mt8195_apusys_pll_drv
ffff8000821a7ab8 d clk_mt8195_cam_drv
ffff8000821a7b80 d clk_mt8195_ccu_drv
ffff8000821a7c48 d clk_mt8195_img_drv
ffff8000821a7d10 d clk_mt8195_imp_iic_wrap_drv
ffff8000821a7dd8 d clk_mt8195_ipe_drv
ffff8000821a7ea0 d clk_mt8195_mfg_drv
ffff8000821a7f68 d clk_mt8195_scp_adsp_drv
ffff8000821a8030 d clk_mt8195_vdec_drv
ffff8000821a80f8 d clk_mt8195_vdo0_drv
ffff8000821a81c0 d clk_mt8195_vdo1_drv
ffff8000821a8288 d clk_mt8195_venc_drv
ffff8000821a8350 d clk_mt8195_vpp0_drv
ffff8000821a8418 d clk_mt8195_vpp1_drv
ffff8000821a84e0 d clk_mt8195_wpe_drv
ffff8000821a85a8 d clk_mt8196_apmixed_drv
ffff8000821a8670 d clk_mt8196_topck_drv
ffff8000821a8738 d clk_mt8196_topck_drv
ffff8000821a8800 d clk_mt8196_vlp_drv
ffff8000821a88c8 d clk_mt8196_peri_ao_drv
ffff8000821a8990 d clk_mt8196_imp_iic_wrap_drv
ffff8000821a8a58 d clk_mt8196_mcu_drv
ffff8000821a8b20 d clk_mt8196_mdpsys_drv
ffff8000821a8be8 d clk_mt8196_pextp_drv
ffff8000821a8cb0 d pext1_rst_idx_map
ffff8000821a8cb8 d pext_rst_idx_map
ffff8000821a8cc0 d pext_rst_ofs
ffff8000821a8cc8 d clk_mt8196_ufs_ao_drv
ffff8000821a8d90 d ufsao_rst_idx_map
ffff8000821a8d98 d ufsao_rst_ofs
ffff8000821a8da0 d clk_mt8365_apmixed_drv
ffff8000821a8e68 d clk_mt8365_drv
ffff8000821a8f30 d mcu_muxes
ffff8000821a8f68 d top_misc_muxes
ffff8000821a9128 d clk_mt8365_apu_drv
ffff8000821a91f0 d clk_mt8365_cam_drv
ffff8000821a92b8 d clk_mt8365_mfg_drv
ffff8000821a9380 d clk_mt8365_mm_drv
ffff8000821a9448 d clk_mt8365_vdec_drv
ffff8000821a9510 d clk_mt8365_venc_drv
ffff8000821a95d8 d clk_mt8516_apmixed_drv
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ffff800082603060 B __SCK__lsm_static_call_msg_queue_msgctl_2
ffff800082603068 B __SCK__lsm_static_call_msg_queue_msgctl_3
ffff800082603070 B __SCK__lsm_static_call_msg_queue_msgctl_4
ffff800082603078 B __SCK__lsm_static_call_msg_queue_msgctl_5
ffff800082603080 B __SCK__lsm_static_call_msg_queue_msgsnd_0
ffff800082603088 B __SCK__lsm_static_call_msg_queue_msgsnd_1
ffff800082603090 B __SCK__lsm_static_call_msg_queue_msgsnd_2
ffff800082603098 B __SCK__lsm_static_call_msg_queue_msgsnd_3
ffff8000826030a0 B __SCK__lsm_static_call_msg_queue_msgsnd_4
ffff8000826030a8 B __SCK__lsm_static_call_msg_queue_msgsnd_5
ffff8000826030b0 B __SCK__lsm_static_call_msg_queue_msgrcv_0
ffff8000826030b8 B __SCK__lsm_static_call_msg_queue_msgrcv_1
ffff8000826030c0 B __SCK__lsm_static_call_msg_queue_msgrcv_2
ffff8000826030c8 B __SCK__lsm_static_call_msg_queue_msgrcv_3
ffff8000826030d0 B __SCK__lsm_static_call_msg_queue_msgrcv_4
ffff8000826030d8 B __SCK__lsm_static_call_msg_queue_msgrcv_5
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ffff8000826030e8 B __SCK__lsm_static_call_shm_free_security_1
ffff8000826030f0 B __SCK__lsm_static_call_shm_free_security_2
ffff8000826030f8 B __SCK__lsm_static_call_shm_free_security_3
ffff800082603100 B __SCK__lsm_static_call_shm_free_security_4
ffff800082603108 B __SCK__lsm_static_call_shm_free_security_5
ffff800082603110 B __SCK__lsm_static_call_shm_alloc_security_0
ffff800082603118 B __SCK__lsm_static_call_shm_alloc_security_1
ffff800082603120 B __SCK__lsm_static_call_shm_alloc_security_2
ffff800082603128 B __SCK__lsm_static_call_shm_alloc_security_3
ffff800082603130 B __SCK__lsm_static_call_shm_alloc_security_4
ffff800082603138 B __SCK__lsm_static_call_shm_alloc_security_5
ffff800082603140 B __SCK__lsm_static_call_shm_associate_0
ffff800082603148 B __SCK__lsm_static_call_shm_associate_1
ffff800082603150 B __SCK__lsm_static_call_shm_associate_2
ffff800082603158 B __SCK__lsm_static_call_shm_associate_3
ffff800082603160 B __SCK__lsm_static_call_shm_associate_4
ffff800082603168 B __SCK__lsm_static_call_shm_associate_5
ffff800082603170 B __SCK__lsm_static_call_shm_shmctl_0
ffff800082603178 B __SCK__lsm_static_call_shm_shmctl_1
ffff800082603180 B __SCK__lsm_static_call_shm_shmctl_2
ffff800082603188 B __SCK__lsm_static_call_shm_shmctl_3
ffff800082603190 B __SCK__lsm_static_call_shm_shmctl_4
ffff800082603198 B __SCK__lsm_static_call_shm_shmctl_5
ffff8000826031a0 B __SCK__lsm_static_call_shm_shmat_0
ffff8000826031a8 B __SCK__lsm_static_call_shm_shmat_1
ffff8000826031b0 B __SCK__lsm_static_call_shm_shmat_2
ffff8000826031b8 B __SCK__lsm_static_call_shm_shmat_3
ffff8000826031c0 B __SCK__lsm_static_call_shm_shmat_4
ffff8000826031c8 B __SCK__lsm_static_call_shm_shmat_5
ffff8000826031d0 B __SCK__lsm_static_call_sem_free_security_0
ffff8000826031d8 B __SCK__lsm_static_call_sem_free_security_1
ffff8000826031e0 B __SCK__lsm_static_call_sem_free_security_2
ffff8000826031e8 B __SCK__lsm_static_call_sem_free_security_3
ffff8000826031f0 B __SCK__lsm_static_call_sem_free_security_4
ffff8000826031f8 B __SCK__lsm_static_call_sem_free_security_5
ffff800082603200 B __SCK__lsm_static_call_sem_alloc_security_0
ffff800082603208 B __SCK__lsm_static_call_sem_alloc_security_1
ffff800082603210 B __SCK__lsm_static_call_sem_alloc_security_2
ffff800082603218 B __SCK__lsm_static_call_sem_alloc_security_3
ffff800082603220 B __SCK__lsm_static_call_sem_alloc_security_4
ffff800082603228 B __SCK__lsm_static_call_sem_alloc_security_5
ffff800082603230 B __SCK__lsm_static_call_sem_associate_0
ffff800082603238 B __SCK__lsm_static_call_sem_associate_1
ffff800082603240 B __SCK__lsm_static_call_sem_associate_2
ffff800082603248 B __SCK__lsm_static_call_sem_associate_3
ffff800082603250 B __SCK__lsm_static_call_sem_associate_4
ffff800082603258 B __SCK__lsm_static_call_sem_associate_5
ffff800082603260 B __SCK__lsm_static_call_sem_semctl_0
ffff800082603268 B __SCK__lsm_static_call_sem_semctl_1
ffff800082603270 B __SCK__lsm_static_call_sem_semctl_2
ffff800082603278 B __SCK__lsm_static_call_sem_semctl_3
ffff800082603280 B __SCK__lsm_static_call_sem_semctl_4
ffff800082603288 B __SCK__lsm_static_call_sem_semctl_5
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ffff800082603298 B __SCK__lsm_static_call_sem_semop_1
ffff8000826032a0 B __SCK__lsm_static_call_sem_semop_2
ffff8000826032a8 B __SCK__lsm_static_call_sem_semop_3
ffff8000826032b0 B __SCK__lsm_static_call_sem_semop_4
ffff8000826032b8 B __SCK__lsm_static_call_sem_semop_5
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ffff8000826032c8 B __SCK__lsm_static_call_netlink_send_1
ffff8000826032d0 B __SCK__lsm_static_call_netlink_send_2
ffff8000826032d8 B __SCK__lsm_static_call_netlink_send_3
ffff8000826032e0 B __SCK__lsm_static_call_netlink_send_4
ffff8000826032e8 B __SCK__lsm_static_call_netlink_send_5
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ffff800082603300 B __SCK__lsm_static_call_socket_create_2
ffff800082603308 B __SCK__lsm_static_call_socket_create_3
ffff800082603310 B __SCK__lsm_static_call_socket_create_4
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ffff800082603338 B __SCK__lsm_static_call_socket_post_create_3
ffff800082603340 B __SCK__lsm_static_call_socket_post_create_4
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